Searched refs:CSR_WRITE_1 (Results 1 - 25 of 48) sorted by relevance

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/freebsd-9.3-release/sys/dev/ex/
H A Dif_ex.c326 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
329 CSR_WRITE_1(sc, EEPROM_REG, temp_reg & ~Trnoff_Enable);
331 CSR_WRITE_1(sc, I_ADDR_REG0 + i, IF_LLADDR(sc->ifp)[i]);
339 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | Tx_Chn_ErStp | Disc_Bad_Fr);
340 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | RX_CRC_InMem);
341 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3) & 0x3f /* XXX constants. */ );
347 CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
349 CSR_WRITE_1(sc, INT_NO_REG,
364 CSR_WRITE_1(sc, RCV_LOWER_LIMIT_REG, sc->rx_lower_limit >> 8);
365 CSR_WRITE_1(s
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H A Dif_ex_isa.c154 CSR_WRITE_1(&sc, CMD_REG, Reset_CMD);
166 CSR_WRITE_1(&sc, CMD_REG, Reset_CMD);
234 CSR_WRITE_1(sc, CMD_REG, Reset_CMD);
H A Dif_exvar.h97 #define CSR_WRITE_1(sc, off, val) \ macro
/freebsd-9.3-release/sys/dev/vge/
H A Dif_vge.c252 CSR_WRITE_1(sc, VGE_EEADDR, addr);
309 CSR_WRITE_1(sc, VGE_MIICMD, 0);
328 CSR_WRITE_1(sc, VGE_MIICMD, 0);
329 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
344 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
370 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
403 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
441 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
443 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
447 CSR_WRITE_1(s
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H A Dif_vgevar.h221 #define CSR_WRITE_1(sc, reg, val) \ macro
232 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
239 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd-9.3-release/sys/dev/sn/
H A Dif_sn.c309 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
338 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
467 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
487 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
499 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
500 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
523 CSR_WRITE_1(sc, DATA_REG_B,
535 CSR_WRITE_1(sc, DATA_REG_B, 0);
549 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
670 CSR_WRITE_1(s
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H A Dif_snvar.h60 #define CSR_WRITE_1(sc, off, val) \ macro
/freebsd-9.3-release/sys/dev/vr/
H A Dif_vr.c248 CSR_WRITE_1(sc, VR_MIIADDR, reg);
271 CSR_WRITE_1(sc, VR_MIIADDR, reg);
342 CSR_WRITE_1(sc, VR_CR1, cr1);
357 CSR_WRITE_1(sc, VR_FLOWCR1, fc);
365 CSR_WRITE_1(sc, VR_MISC_CR0, fc);
385 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
387 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
389 CSR_WRITE_1(sc, VR_CAMCTL, 0);
400 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
402 CSR_WRITE_1(s
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H A Dif_vrreg.h752 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->vr_res, reg, val) macro
757 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
758 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd-9.3-release/sys/dev/vx/
H A Dif_vxvar.h64 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd-9.3-release/sys/dev/re/
H A Dif_re.c346 CSR_WRITE_1(sc, RL_EECMD, \
350 CSR_WRITE_1(sc, RL_EECMD, \
718 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
729 CSR_WRITE_1(sc, 0x82, 1);
1305 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1308 CSR_WRITE_1(sc, RL_CFG2, cfg);
1309 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1342 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1347 CSR_WRITE_1(sc, RL_CFG2, cfg);
1349 CSR_WRITE_1(s
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/freebsd-9.3-release/sys/pci/
H A Dif_rl.c265 CSR_WRITE_1(sc, RL_EECMD, \
269 CSR_WRITE_1(sc, RL_EECMD, \
309 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
316 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
331 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
383 CSR_WRITE_1(sc, RL_MII, val);
567 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
1717 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1722 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1735 CSR_WRITE_1(s
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/freebsd-9.3-release/sys/dev/msk/
H A Dif_msk.c511 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
1256 CSR_WRITE_1(sc, B0_POWER_CTRL,
1272 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1340 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1341 CSR_WRITE_1(sc, B0_POWER_CTRL,
1373 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1385 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1422 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1423 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1442 CSR_WRITE_1(s
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/freebsd-9.3-release/sys/dev/bm/
H A Dif_bmreg.h159 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd-9.3-release/sys/dev/tx/
H A Dif_txvar.h134 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd-9.3-release/sys/dev/ep/
H A Dif_epvar.h88 #define CSR_WRITE_1(sc, off, val) \ macro
H A Dif_ep.c274 CSR_WRITE_1(sc, EP_W2_ADDR_0 + i, enaddr[i]);
552 CSR_WRITE_1(sc, EP_W1_TX_PIO_WR_1,
558 CSR_WRITE_1(sc, EP_W1_TX_PIO_WR_1, 0); /* Padding */
697 CSR_WRITE_1(sc, EP_W1_TX_STATUS, 0x0);
/freebsd-9.3-release/sys/dev/fxp/
H A Dif_fxpvar.h246 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val) macro
/freebsd-9.3-release/sys/dev/ipw/
H A Dif_ipwreg.h334 #define CSR_WRITE_1(sc, reg, val) \ macro
360 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
/freebsd-9.3-release/sys/dev/ste/
H A Dif_ste.c196 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
199 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
229 CSR_WRITE_1(sc, STE_PHYCTL, val);
451 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
1538 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1547 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
1550 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1556 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1573 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1642 CSR_WRITE_1(s
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/freebsd-9.3-release/sys/dev/stge/
H A Dif_stge.c274 CSR_WRITE_1(sc, STGE_PhyCtrl, val);
998 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1041 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1964 CSR_WRITE_1(sc, STGE_PhySet, v);
2059 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2062 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2068 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2069 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2075 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2076 CSR_WRITE_1(s
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/freebsd-9.3-release/sys/dev/iwi/
H A Dif_iwireg.h521 #define CSR_WRITE_1(sc, reg, val) \ macro
539 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/freebsd-9.3-release/sys/dev/alc/
H A Dif_alcvar.h257 #define CSR_WRITE_1(_sc, reg, val) \ macro
/freebsd-9.3-release/sys/dev/ale/
H A Dif_alevar.h233 #define CSR_WRITE_1(_sc, reg, val) \ macro
/freebsd-9.3-release/sys/dev/xl/
H A Dif_xl.c467 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
811 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
815 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
2106 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2120 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2143 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2713 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2754 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2794 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2827 CSR_WRITE_1(s
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