1139825Simp/*- 2119868Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul */ 3240516Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD$"); 35122678Sobrien 3640516Swpaul/* 37119868Swpaul * RealTek 8129/8139 PCI NIC driver 3840516Swpaul * 39119868Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 40119868Swpaul * the RealTek chipset. Datasheets can be obtained from 4140516Swpaul * www.realtek.com.tw. 4240516Swpaul * 43119868Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 44119868Swpaul * Electrical Engineering Department 45119868Swpaul * Columbia University, New York City 4640516Swpaul */ 4740516Swpaul/* 4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5240516Swpaul * gains that bus-master DMA usually offers. 5340516Swpaul * 5440516Swpaul * For transmission, the chip offers a series of four TX descriptor 5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5641569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 6040516Swpaul * four descriptor registers means that we can never have more than four 6140516Swpaul * packets queued for transmission at any one time. 6240516Swpaul * 6340516Swpaul * Reception is not much better. The driver has to allocate a single large 6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6540516Swpaul * frames. Because we don't know where within this region received packets 6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6840516Swpaul * levels. 6940516Swpaul * 7040516Swpaul * It's impossible given this rotten design to really achieve decent 7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7240516Swpaul * some equally overmuscled CPU to drive it. 7340516Swpaul * 7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7640516Swpaul * PHY registers are directly accessible through the 8139's register 7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7840516Swpaul * filter. 7940516Swpaul * 8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8340516Swpaul * to select which interface to use depending on the chip type. 8440516Swpaul */ 8540516Swpaul 86150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 87150968Sglebius#include "opt_device_polling.h" 88150968Sglebius#endif 89150968Sglebius 9040516Swpaul#include <sys/param.h> 91108729Sjake#include <sys/endian.h> 9240516Swpaul#include <sys/systm.h> 9340516Swpaul#include <sys/sockio.h> 9440516Swpaul#include <sys/mbuf.h> 9540516Swpaul#include <sys/malloc.h> 9640516Swpaul#include <sys/kernel.h> 97129878Sphk#include <sys/module.h> 9840516Swpaul#include <sys/socket.h> 99184559Simp#include <sys/sysctl.h> 10040516Swpaul 10140516Swpaul#include <net/if.h> 10240516Swpaul#include <net/if_arp.h> 10340516Swpaul#include <net/ethernet.h> 10440516Swpaul#include <net/if_dl.h> 10540516Swpaul#include <net/if_media.h> 106147256Sbrooks#include <net/if_types.h> 10740516Swpaul 10840516Swpaul#include <net/bpf.h> 10940516Swpaul 11041569Swpaul#include <machine/bus.h> 11150703Swpaul#include <machine/resource.h> 11250703Swpaul#include <sys/bus.h> 11350703Swpaul#include <sys/rman.h> 11440516Swpaul 11550703Swpaul#include <dev/mii/mii.h> 116227277Smarius#include <dev/mii/mii_bitbang.h> 11750703Swpaul#include <dev/mii/miivar.h> 11850703Swpaul 119119871Swpaul#include <dev/pci/pcireg.h> 120119871Swpaul#include <dev/pci/pcivar.h> 12140516Swpaul 122113506SmdoddMODULE_DEPEND(rl, pci, 1, 1, 1); 123113506SmdoddMODULE_DEPEND(rl, ether, 1, 1, 1); 12459758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 12559758Speter 126151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 12750703Swpaul#include "miibus_if.h" 12850703Swpaul 12940516Swpaul#include <pci/if_rlreg.h> 13040516Swpaul 13140516Swpaul/* 13240516Swpaul * Various supported device vendors/types and their names. 13340516Swpaul */ 134242908Sdimstatic const struct rl_type rl_devs[] = { 135117388Swpaul { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 13640516Swpaul "RealTek 8129 10/100BaseTX" }, 137117388Swpaul { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 13840516Swpaul "RealTek 8139 10/100BaseTX" }, 139179831Sremko { RT_VENDORID, RT_DEVICEID_8139D, RL_8139, 140179831Sremko "RealTek 8139 10/100BaseTX" }, 141117388Swpaul { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 14267771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 143118978Swpaul { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 144118978Swpaul "RealTek 8100 10/100BaseTX" }, 145117388Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 14641243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 147117388Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 14844238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 149117388Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 150184524Simp "Addtron Technology 8139 10/100BaseTX" }, 151245857Syongari { DLINK_VENDORID, DLINK_DEVICEID_520TX_REVC1, RL_8139, 152245857Syongari "D-Link DFE-520TX (rev. C1) 10/100BaseTX" }, 153117388Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 15472813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 155117388Swpaul { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 15696112Sjhb "D-Link DFE-690TXD 10/100BaseTX" }, 157117388Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 15894400Swpaul "Nortel Networks 10/100BaseTX" }, 159117388Swpaul { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 160103020Siwasaki "Corega FEther CB-TXD" }, 161117388Swpaul { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 162109095Ssanpei "Corega FEtherII CB-TXD" }, 163117388Swpaul { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 164111381Sdan "Peppercon AG ROL-F" }, 165173948Sremko { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139, 166173948Sremko "Planex FNW-3603-TX" }, 167117388Swpaul { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 168112379Ssanpei "Planex FNW-3800-TX" }, 169117388Swpaul { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 170117388Swpaul "Compaq HNE-300" }, 171117388Swpaul { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 172117388Swpaul "LevelOne FPC-0106TX" }, 173117388Swpaul { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 174176757Syongari "Edimax EP-4103DL CardBus" } 17540516Swpaul}; 17640516Swpaul 177142407Simpstatic int rl_attach(device_t); 178142407Simpstatic int rl_detach(device_t); 179184240Syongaristatic void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int); 180184240Syongaristatic int rl_dma_alloc(struct rl_softc *); 181184240Syongaristatic void rl_dma_free(struct rl_softc *); 182142407Simpstatic void rl_eeprom_putbyte(struct rl_softc *, int); 183142407Simpstatic void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 184184240Syongaristatic int rl_encap(struct rl_softc *, struct mbuf **); 185142407Simpstatic int rl_list_tx_init(struct rl_softc *); 186184240Syongaristatic int rl_list_rx_init(struct rl_softc *); 187142407Simpstatic int rl_ifmedia_upd(struct ifnet *); 188142407Simpstatic void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 189142407Simpstatic int rl_ioctl(struct ifnet *, u_long, caddr_t); 190142407Simpstatic void rl_intr(void *); 191142407Simpstatic void rl_init(void *); 192142407Simpstatic void rl_init_locked(struct rl_softc *sc); 193142407Simpstatic int rl_miibus_readreg(device_t, int, int); 194142407Simpstatic void rl_miibus_statchg(device_t); 195142407Simpstatic int rl_miibus_writereg(device_t, int, int, int); 196131841Sbms#ifdef DEVICE_POLLING 197193096Sattiliostatic int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 198193096Sattiliostatic int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 199131841Sbms#endif 200142407Simpstatic int rl_probe(device_t); 201142407Simpstatic void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); 202142407Simpstatic void rl_reset(struct rl_softc *); 203142407Simpstatic int rl_resume(device_t); 204193096Sattiliostatic int rl_rxeof(struct rl_softc *); 205213306Syongaristatic void rl_rxfilter(struct rl_softc *); 206173839Syongaristatic int rl_shutdown(device_t); 207142407Simpstatic void rl_start(struct ifnet *); 208142407Simpstatic void rl_start_locked(struct ifnet *); 209142407Simpstatic void rl_stop(struct rl_softc *); 210142407Simpstatic int rl_suspend(device_t); 211142407Simpstatic void rl_tick(void *); 212142407Simpstatic void rl_txeof(struct rl_softc *); 213164811Srustatic void rl_watchdog(struct rl_softc *); 214210244Syongaristatic void rl_setwol(struct rl_softc *); 215210244Syongaristatic void rl_clrwol(struct rl_softc *); 21640516Swpaul 217227277Smarius/* 218227277Smarius * MII bit-bang glue 219227277Smarius */ 220227277Smariusstatic uint32_t rl_mii_bitbang_read(device_t); 221227277Smariusstatic void rl_mii_bitbang_write(device_t, uint32_t); 222227277Smarius 223227277Smariusstatic const struct mii_bitbang_ops rl_mii_bitbang_ops = { 224227277Smarius rl_mii_bitbang_read, 225227277Smarius rl_mii_bitbang_write, 226227277Smarius { 227227277Smarius RL_MII_DATAOUT, /* MII_BIT_MDO */ 228227277Smarius RL_MII_DATAIN, /* MII_BIT_MDI */ 229227277Smarius RL_MII_CLK, /* MII_BIT_MDC */ 230227277Smarius RL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 231227277Smarius 0, /* MII_BIT_DIR_PHY_HOST */ 232227277Smarius } 233227277Smarius}; 234227277Smarius 23550703Swpaulstatic device_method_t rl_methods[] = { 23650703Swpaul /* Device interface */ 23750703Swpaul DEVMETHOD(device_probe, rl_probe), 23850703Swpaul DEVMETHOD(device_attach, rl_attach), 23950703Swpaul DEVMETHOD(device_detach, rl_detach), 24086822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 24186822Siwasaki DEVMETHOD(device_resume, rl_resume), 24250703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 24350703Swpaul 24450703Swpaul /* MII interface */ 24550703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 24650703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 24750703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 24850703Swpaul 249229093Shselasky DEVMETHOD_END 25050703Swpaul}; 25150703Swpaul 25250703Swpaulstatic driver_t rl_driver = { 25351455Swpaul "rl", 25450703Swpaul rl_methods, 25550703Swpaul sizeof(struct rl_softc) 25650703Swpaul}; 25750703Swpaul 25850703Swpaulstatic devclass_t rl_devclass; 25950703Swpaul 260113506SmdoddDRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 261123019SimpDRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 26251473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 26350703Swpaul 26440516Swpaul#define EE_SET(x) \ 26540516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 26640516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 26740516Swpaul 26840516Swpaul#define EE_CLR(x) \ 26940516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 27040516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 27140516Swpaul 27240516Swpaul/* 27340516Swpaul * Send a read command and address to the EEPROM, check for ACK. 27440516Swpaul */ 275102335Salfredstatic void 276131605Sbmsrl_eeprom_putbyte(struct rl_softc *sc, int addr) 27740516Swpaul{ 27840516Swpaul register int d, i; 27940516Swpaul 28067931Swpaul d = addr | sc->rl_eecmd_read; 28140516Swpaul 28240516Swpaul /* 28355170Sbillf * Feed in each bit and strobe the clock. 28440516Swpaul */ 28540516Swpaul for (i = 0x400; i; i >>= 1) { 28640516Swpaul if (d & i) { 28740516Swpaul EE_SET(RL_EE_DATAIN); 28840516Swpaul } else { 28940516Swpaul EE_CLR(RL_EE_DATAIN); 29040516Swpaul } 29140516Swpaul DELAY(100); 29240516Swpaul EE_SET(RL_EE_CLK); 29340516Swpaul DELAY(150); 29440516Swpaul EE_CLR(RL_EE_CLK); 29540516Swpaul DELAY(100); 29640516Swpaul } 29740516Swpaul} 29840516Swpaul 29940516Swpaul/* 30040516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 30140516Swpaul */ 302102335Salfredstatic void 303131605Sbmsrl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 30440516Swpaul{ 30540516Swpaul register int i; 306131605Sbms uint16_t word = 0; 30740516Swpaul 30840516Swpaul /* Enter EEPROM access mode. */ 30940516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 31040516Swpaul 31140516Swpaul /* 31240516Swpaul * Send address of word we want to read. 31340516Swpaul */ 31440516Swpaul rl_eeprom_putbyte(sc, addr); 31540516Swpaul 31640516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 31740516Swpaul 31840516Swpaul /* 31940516Swpaul * Start reading bits from EEPROM. 32040516Swpaul */ 32140516Swpaul for (i = 0x8000; i; i >>= 1) { 32240516Swpaul EE_SET(RL_EE_CLK); 32340516Swpaul DELAY(100); 32440516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 32540516Swpaul word |= i; 32640516Swpaul EE_CLR(RL_EE_CLK); 32740516Swpaul DELAY(100); 32840516Swpaul } 32940516Swpaul 33040516Swpaul /* Turn off EEPROM access mode. */ 33140516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 33240516Swpaul 33340516Swpaul *dest = word; 33440516Swpaul} 33540516Swpaul 33640516Swpaul/* 33740516Swpaul * Read a sequence of words from the EEPROM. 33840516Swpaul */ 339102335Salfredstatic void 340131605Sbmsrl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap) 34140516Swpaul{ 34240516Swpaul int i; 343131605Sbms uint16_t word = 0, *ptr; 34440516Swpaul 34540516Swpaul for (i = 0; i < cnt; i++) { 34640516Swpaul rl_eeprom_getword(sc, off + i, &word); 347131605Sbms ptr = (uint16_t *)(dest + (i * 2)); 34840516Swpaul if (swap) 34940516Swpaul *ptr = ntohs(word); 35040516Swpaul else 35140516Swpaul *ptr = word; 35240516Swpaul } 35340516Swpaul} 35440516Swpaul 35540516Swpaul/* 356227277Smarius * Read the MII serial port for the MII bit-bang module. 35740516Swpaul */ 358227277Smariusstatic uint32_t 359227277Smariusrl_mii_bitbang_read(device_t dev) 360227277Smarius{ 361227277Smarius struct rl_softc *sc; 362227277Smarius uint32_t val; 36340516Swpaul 364227277Smarius sc = device_get_softc(dev); 36540516Swpaul 366227277Smarius val = CSR_READ_1(sc, RL_MII); 367227277Smarius CSR_BARRIER(sc, RL_MII, 1, 368227277Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 36940516Swpaul 370227277Smarius return (val); 37140516Swpaul} 37240516Swpaul 37340516Swpaul/* 374227277Smarius * Write the MII serial port for the MII bit-bang module. 37540516Swpaul */ 376102335Salfredstatic void 377227277Smariusrl_mii_bitbang_write(device_t dev, uint32_t val) 37840516Swpaul{ 379227277Smarius struct rl_softc *sc; 38040516Swpaul 381227277Smarius sc = device_get_softc(dev); 38240516Swpaul 383227277Smarius CSR_WRITE_1(sc, RL_MII, val); 384227277Smarius CSR_BARRIER(sc, RL_MII, 1, 385227277Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 38640516Swpaul} 38740516Swpaul 388102335Salfredstatic int 389131605Sbmsrl_miibus_readreg(device_t dev, int phy, int reg) 39050703Swpaul{ 39140516Swpaul struct rl_softc *sc; 392227277Smarius uint16_t rl8139_reg; 39340516Swpaul 39450703Swpaul sc = device_get_softc(dev); 39550703Swpaul 396119868Swpaul if (sc->rl_type == RL_8139) { 397131605Sbms switch (reg) { 39850703Swpaul case MII_BMCR: 39940516Swpaul rl8139_reg = RL_BMCR; 40040516Swpaul break; 40150703Swpaul case MII_BMSR: 40240516Swpaul rl8139_reg = RL_BMSR; 40340516Swpaul break; 40450703Swpaul case MII_ANAR: 40540516Swpaul rl8139_reg = RL_ANAR; 40640516Swpaul break; 40750703Swpaul case MII_ANER: 40850703Swpaul rl8139_reg = RL_ANER; 40950703Swpaul break; 41050703Swpaul case MII_ANLPAR: 41140516Swpaul rl8139_reg = RL_LPAR; 41240516Swpaul break; 41350703Swpaul case MII_PHYIDR1: 41450703Swpaul case MII_PHYIDR2: 415131605Sbms return (0); 41694149Swpaul /* 41794149Swpaul * Allow the rlphy driver to read the media status 41894149Swpaul * register. If we have a link partner which does not 41994149Swpaul * support NWAY, this is the register which will tell 42094149Swpaul * us the results of parallel detection. 42194149Swpaul */ 42294149Swpaul case RL_MEDIASTAT: 423227277Smarius return (CSR_READ_1(sc, RL_MEDIASTAT)); 42440516Swpaul default: 425162315Sglebius device_printf(sc->rl_dev, "bad phy register\n"); 426131605Sbms return (0); 42740516Swpaul } 428227277Smarius return (CSR_READ_2(sc, rl8139_reg)); 42940516Swpaul } 43040516Swpaul 431227277Smarius return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg)); 43240516Swpaul} 43340516Swpaul 434102335Salfredstatic int 435131605Sbmsrl_miibus_writereg(device_t dev, int phy, int reg, int data) 43650703Swpaul{ 43740516Swpaul struct rl_softc *sc; 438227277Smarius uint16_t rl8139_reg; 43940516Swpaul 44050703Swpaul sc = device_get_softc(dev); 44150703Swpaul 442119868Swpaul if (sc->rl_type == RL_8139) { 443131605Sbms switch (reg) { 44450703Swpaul case MII_BMCR: 44540516Swpaul rl8139_reg = RL_BMCR; 44640516Swpaul break; 44750703Swpaul case MII_BMSR: 44840516Swpaul rl8139_reg = RL_BMSR; 44940516Swpaul break; 45050703Swpaul case MII_ANAR: 45140516Swpaul rl8139_reg = RL_ANAR; 45240516Swpaul break; 45350703Swpaul case MII_ANER: 45450703Swpaul rl8139_reg = RL_ANER; 45550703Swpaul break; 45650703Swpaul case MII_ANLPAR: 45740516Swpaul rl8139_reg = RL_LPAR; 45840516Swpaul break; 45950703Swpaul case MII_PHYIDR1: 46050703Swpaul case MII_PHYIDR2: 461131605Sbms return (0); 46250703Swpaul break; 46340516Swpaul default: 464162315Sglebius device_printf(sc->rl_dev, "bad phy register\n"); 465131605Sbms return (0); 46640516Swpaul } 46740516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 468131605Sbms return (0); 46940516Swpaul } 47040516Swpaul 471227277Smarius mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data); 47240516Swpaul 473131605Sbms return (0); 47450703Swpaul} 47550703Swpaul 476102335Salfredstatic void 477131605Sbmsrl_miibus_statchg(device_t dev) 47850703Swpaul{ 479184245Syongari struct rl_softc *sc; 480184245Syongari struct ifnet *ifp; 481184245Syongari struct mii_data *mii; 482184245Syongari 483184245Syongari sc = device_get_softc(dev); 484184245Syongari mii = device_get_softc(sc->rl_miibus); 485184245Syongari ifp = sc->rl_ifp; 486184245Syongari if (mii == NULL || ifp == NULL || 487184245Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 488184245Syongari return; 489184245Syongari 490184245Syongari sc->rl_flags &= ~RL_FLAG_LINK; 491184245Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 492184245Syongari (IFM_ACTIVE | IFM_AVALID)) { 493184245Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 494184245Syongari case IFM_10_T: 495184245Syongari case IFM_100_TX: 496184245Syongari sc->rl_flags |= RL_FLAG_LINK; 497184245Syongari break; 498184245Syongari default: 499184245Syongari break; 500184245Syongari } 501184245Syongari } 502184245Syongari /* 503184245Syongari * RealTek controllers do not provide any interface to 504184245Syongari * Tx/Rx MACs for resolved speed, duplex and flow-control 505184245Syongari * parameters. 506184245Syongari */ 50740516Swpaul} 50840516Swpaul 50940516Swpaul/* 51040516Swpaul * Program the 64-bit multicast hash filter. 51140516Swpaul */ 512102335Salfredstatic void 513213306Syongarirl_rxfilter(struct rl_softc *sc) 51440516Swpaul{ 515147256Sbrooks struct ifnet *ifp = sc->rl_ifp; 51640516Swpaul int h = 0; 517131605Sbms uint32_t hashes[2] = { 0, 0 }; 51840516Swpaul struct ifmultiaddr *ifma; 519131605Sbms uint32_t rxfilt; 52040516Swpaul 521131606Sbms RL_LOCK_ASSERT(sc); 522131606Sbms 52340516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 524213306Syongari rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD | 525213306Syongari RL_RXCFG_RX_MULTI); 526213306Syongari /* Always accept frames destined for this host. */ 527213306Syongari rxfilt |= RL_RXCFG_RX_INDIV; 528213306Syongari /* Set capture broadcast bit to capture broadcast frames. */ 529213306Syongari if (ifp->if_flags & IFF_BROADCAST) 530213306Syongari rxfilt |= RL_RXCFG_RX_BROAD; 53143062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 53240516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 533213306Syongari if (ifp->if_flags & IFF_PROMISC) 534213306Syongari rxfilt |= RL_RXCFG_RX_ALLPHYS; 535213306Syongari hashes[0] = 0xFFFFFFFF; 536213306Syongari hashes[1] = 0xFFFFFFFF; 537213306Syongari } else { 538213306Syongari /* Now program new ones. */ 539213306Syongari if_maddr_rlock(ifp); 540213306Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 541213306Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 542213306Syongari continue; 543213306Syongari h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 544213306Syongari ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 545213306Syongari if (h < 32) 546213306Syongari hashes[0] |= (1 << h); 547213306Syongari else 548213306Syongari hashes[1] |= (1 << (h - 32)); 549213306Syongari } 550213306Syongari if_maddr_runlock(ifp); 551213306Syongari if (hashes[0] != 0 || hashes[1] != 0) 552213306Syongari rxfilt |= RL_RXCFG_RX_MULTI; 55340516Swpaul } 55440516Swpaul 55540516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 55640516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 557213306Syongari CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 55840516Swpaul} 55940516Swpaul 560102335Salfredstatic void 561131605Sbmsrl_reset(struct rl_softc *sc) 56240516Swpaul{ 56340516Swpaul register int i; 56440516Swpaul 565131606Sbms RL_LOCK_ASSERT(sc); 566131606Sbms 56740516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 56840516Swpaul 56940516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 57040516Swpaul DELAY(10); 57140516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 57240516Swpaul break; 57340516Swpaul } 57440516Swpaul if (i == RL_TIMEOUT) 575162315Sglebius device_printf(sc->rl_dev, "reset never completed!\n"); 57640516Swpaul} 57740516Swpaul 57840516Swpaul/* 57940516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 58040516Swpaul * IDs against our list and return a device name if we find a match. 58140516Swpaul */ 582102335Salfredstatic int 583131605Sbmsrl_probe(device_t dev) 58440516Swpaul{ 585227277Smarius const struct rl_type *t; 586176757Syongari uint16_t devid, revid, vendor; 587176757Syongari int i; 588176757Syongari 589176757Syongari vendor = pci_get_vendor(dev); 590176757Syongari devid = pci_get_device(dev); 591176757Syongari revid = pci_get_revid(dev); 59240516Swpaul 593176757Syongari if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 594176757Syongari if (revid == 0x20) { 595176757Syongari /* 8139C+, let re(4) take care of this device. */ 596176757Syongari return (ENXIO); 597176757Syongari } 598176757Syongari } 599176757Syongari t = rl_devs; 600176757Syongari for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) { 601176757Syongari if (vendor == t->rl_vid && devid == t->rl_did) { 602119868Swpaul device_set_desc(dev, t->rl_name); 603142398Simp return (BUS_PROBE_DEFAULT); 60440516Swpaul } 60540516Swpaul } 60640516Swpaul 607131605Sbms return (ENXIO); 60840516Swpaul} 60940516Swpaul 610184240Syongaristruct rl_dmamap_arg { 611184240Syongari bus_addr_t rl_busaddr; 612184240Syongari}; 613184240Syongari 614184240Syongaristatic void 615184240Syongarirl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 616184240Syongari{ 617184240Syongari struct rl_dmamap_arg *ctx; 618184240Syongari 619184240Syongari if (error != 0) 620184240Syongari return; 621184240Syongari 622184240Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 623184240Syongari 624184240Syongari ctx = (struct rl_dmamap_arg *)arg; 625184240Syongari ctx->rl_busaddr = segs[0].ds_addr; 626184240Syongari} 627184240Syongari 62840516Swpaul/* 62940516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 63040516Swpaul * setup and ethernet/BPF attach. 63140516Swpaul */ 632102335Salfredstatic int 633131605Sbmsrl_attach(device_t dev) 63440516Swpaul{ 635131605Sbms uint8_t eaddr[ETHER_ADDR_LEN]; 636131605Sbms uint16_t as[3]; 637131605Sbms struct ifnet *ifp; 63840516Swpaul struct rl_softc *sc; 639227277Smarius const struct rl_type *t; 640184559Simp struct sysctl_ctx_list *ctx; 641184559Simp struct sysctl_oid_list *children; 642213893Smarius int error = 0, hwrev, i, phy, pmc, rid; 643211648Syongari int prefer_iomap, unit; 644131605Sbms uint16_t rl_did = 0; 645184559Simp char tn[32]; 64640516Swpaul 64750703Swpaul sc = device_get_softc(dev); 64850703Swpaul unit = device_get_unit(dev); 649162315Sglebius sc->rl_dev = dev; 65040516Swpaul 651184559Simp sc->rl_twister_enable = 0; 652184559Simp snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit); 653184559Simp TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable); 654184559Simp ctx = device_get_sysctl_ctx(sc->rl_dev); 655184559Simp children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 656184559Simp SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD, 657184559Simp &sc->rl_twister_enable, 0, ""); 658184559Simp 65993818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 660131606Sbms MTX_DEF); 661150720Sjhb callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 662131605Sbms 66372813Swpaul pci_enable_busmaster(dev); 66440516Swpaul 66550703Swpaul 666211648Syongari /* 667211648Syongari * Map control/status registers. 668211648Syongari * Default to using PIO access for this driver. On SMP systems, 669211648Syongari * there appear to be problems with memory mapped mode: it looks 670211648Syongari * like doing too many memory mapped access back to back in rapid 671211648Syongari * succession can hang the bus. I'm inclined to blame this on 672211648Syongari * crummy design/construction on the part of RealTek. Memory 673211648Syongari * mapped mode does appear to work on uniprocessor systems though. 674211648Syongari */ 675211648Syongari prefer_iomap = 1; 676211648Syongari snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit); 677211648Syongari TUNABLE_INT_FETCH(tn, &prefer_iomap); 678211648Syongari if (prefer_iomap) { 679211648Syongari sc->rl_res_id = PCIR_BAR(0); 680211648Syongari sc->rl_res_type = SYS_RES_IOPORT; 681211648Syongari sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 682211648Syongari &sc->rl_res_id, RF_ACTIVE); 683211648Syongari } 684211648Syongari if (prefer_iomap == 0 || sc->rl_res == NULL) { 685211648Syongari sc->rl_res_id = PCIR_BAR(1); 686211648Syongari sc->rl_res_type = SYS_RES_MEMORY; 687211648Syongari sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 688211648Syongari &sc->rl_res_id, RF_ACTIVE); 689211648Syongari } 69050703Swpaul if (sc->rl_res == NULL) { 691131605Sbms device_printf(dev, "couldn't map ports/memory\n"); 69250703Swpaul error = ENXIO; 69340516Swpaul goto fail; 69440516Swpaul } 69540516Swpaul 696117388Swpaul#ifdef notdef 697131605Sbms /* 698131605Sbms * Detect the Realtek 8139B. For some reason, this chip is very 69969127Sroger * unstable when left to autoselect the media 70069127Sroger * The best workaround is to set the device to the required 70169127Sroger * media type or to set it to the 10 Meg speed. 70269127Sroger */ 703131605Sbms if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) 704131605Sbms device_printf(dev, 705131605Sbms"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n"); 706117388Swpaul#endif 70769127Sroger 70850703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 70950703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 71050703Swpaul 711112872Snjl /* Allocate interrupt */ 71250703Swpaul rid = 0; 713171560Syongari sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 71450703Swpaul RF_SHAREABLE | RF_ACTIVE); 71550703Swpaul 716171560Syongari if (sc->rl_irq[0] == NULL) { 717131605Sbms device_printf(dev, "couldn't map interrupt\n"); 71850703Swpaul error = ENXIO; 71940516Swpaul goto fail; 72040516Swpaul } 72140516Swpaul 722233489Syongari sc->rl_cfg0 = RL_8139_CFG0; 723233489Syongari sc->rl_cfg1 = RL_8139_CFG1; 724233489Syongari sc->rl_cfg2 = 0; 725233489Syongari sc->rl_cfg3 = RL_8139_CFG3; 726233489Syongari sc->rl_cfg4 = RL_8139_CFG4; 727233489Syongari sc->rl_cfg5 = RL_8139_CFG5; 728233489Syongari 729131606Sbms /* 730131606Sbms * Reset the adapter. Only take the lock here as it's needed in 731131606Sbms * order to call rl_reset(). 732131606Sbms */ 733131606Sbms RL_LOCK(sc); 73440516Swpaul rl_reset(sc); 735131606Sbms RL_UNLOCK(sc); 736131606Sbms 73767931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 738131605Sbms rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 73968215Swpaul if (rl_did != 0x8129) 74067931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 74140516Swpaul 74240516Swpaul /* 74340516Swpaul * Get station address from the EEPROM. 74440516Swpaul */ 745131605Sbms rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0); 746108729Sjake for (i = 0; i < 3; i++) { 747108729Sjake eaddr[(i * 2) + 0] = as[i] & 0xff; 748108729Sjake eaddr[(i * 2) + 1] = as[i] >> 8; 749108729Sjake } 75040516Swpaul 75140516Swpaul /* 75240516Swpaul * Now read the exact device type from the EEPROM to find 75340516Swpaul * out if it's an 8129 or 8139. 75440516Swpaul */ 755131605Sbms rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0); 75640516Swpaul 757117388Swpaul t = rl_devs; 758119868Swpaul sc->rl_type = 0; 759117388Swpaul while(t->rl_name != NULL) { 760117388Swpaul if (rl_did == t->rl_did) { 761117388Swpaul sc->rl_type = t->rl_basetype; 762117388Swpaul break; 763117388Swpaul } 764117388Swpaul t++; 765117388Swpaul } 766119868Swpaul 767119868Swpaul if (sc->rl_type == 0) { 768186142Swilko device_printf(dev, "unknown device ID: %x assuming 8139\n", 769186142Swilko rl_did); 770186142Swilko sc->rl_type = RL_8139; 771186142Swilko /* 772186142Swilko * Read RL_IDR register to get ethernet address as accessing 773186142Swilko * EEPROM may not extract correct address. 774186142Swilko */ 775186142Swilko for (i = 0; i < ETHER_ADDR_LEN; i++) 776186142Swilko eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 77740516Swpaul } 77840516Swpaul 779184240Syongari if ((error = rl_dma_alloc(sc)) != 0) 780112872Snjl goto fail; 78140516Swpaul 782147291Sbrooks ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 783147291Sbrooks if (ifp == NULL) { 784147291Sbrooks device_printf(dev, "can not if_alloc()\n"); 785147291Sbrooks error = ENOSPC; 786147291Sbrooks goto fail; 787147291Sbrooks } 788147291Sbrooks 789213893Smarius#define RL_PHYAD_INTERNAL 0 790213893Smarius 79150703Swpaul /* Do MII setup */ 792213893Smarius phy = MII_PHY_ANY; 793213893Smarius if (sc->rl_type == RL_8139) 794213893Smarius phy = RL_PHYAD_INTERNAL; 795213893Smarius error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd, 796213893Smarius rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 797213893Smarius if (error != 0) { 798213893Smarius device_printf(dev, "attaching PHYs failed\n"); 79950703Swpaul goto fail; 80050703Swpaul } 80150703Swpaul 80240516Swpaul ifp->if_softc = sc; 803121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 80440516Swpaul ifp->if_mtu = ETHERMTU; 80540516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 80640516Swpaul ifp->if_ioctl = rl_ioctl; 807119868Swpaul ifp->if_start = rl_start; 80840516Swpaul ifp->if_init = rl_init; 809119976Swpaul ifp->if_capabilities = IFCAP_VLAN_MTU; 810210244Syongari /* Check WOL for RTL8139B or newer controllers. */ 811210244Syongari if (sc->rl_type == RL_8139 && 812219902Sjhb pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { 813210244Syongari hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 814210244Syongari switch (hwrev) { 815210244Syongari case RL_HWREV_8139B: 816210244Syongari case RL_HWREV_8130: 817210244Syongari case RL_HWREV_8139C: 818210244Syongari case RL_HWREV_8139D: 819210244Syongari case RL_HWREV_8101: 820210244Syongari case RL_HWREV_8100: 821210244Syongari ifp->if_capabilities |= IFCAP_WOL; 822210244Syongari /* Disable WOL. */ 823210244Syongari rl_clrwol(sc); 824210244Syongari break; 825210244Syongari default: 826210244Syongari break; 827210244Syongari } 828210244Syongari } 829150789Sglebius ifp->if_capenable = ifp->if_capabilities; 830233489Syongari ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 831128121Sru#ifdef DEVICE_POLLING 832128121Sru ifp->if_capabilities |= IFCAP_POLLING; 833128121Sru#endif 834207554Ssobomax IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 835207554Ssobomax ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 836131455Smlaier IFQ_SET_READY(&ifp->if_snd); 837131605Sbms 83840516Swpaul /* 83963090Sarchie * Call MI attach routine. 84040516Swpaul */ 841106936Ssam ether_ifattach(ifp, eaddr); 842106157Simp 843113609Snjl /* Hook interrupt last to avoid having to lock softc */ 844171560Syongari error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE, 845171560Syongari NULL, rl_intr, sc, &sc->rl_intrhand[0]); 846106157Simp if (error) { 847162315Sglebius device_printf(sc->rl_dev, "couldn't set up irq\n"); 848113609Snjl ether_ifdetach(ifp); 849106157Simp } 850106157Simp 85140516Swpaulfail: 852112872Snjl if (error) 853112872Snjl rl_detach(dev); 854112872Snjl 855110601Snjl return (error); 85640516Swpaul} 85740516Swpaul 858113609Snjl/* 859113609Snjl * Shutdown hardware and free up resources. This can be called any 860113609Snjl * time after the mutex has been initialized. It is called in both 861113609Snjl * the error case in attach and the normal detach case so it needs 862113609Snjl * to be careful about only freeing resources that have actually been 863113609Snjl * allocated. 864113609Snjl */ 865102335Salfredstatic int 866131605Sbmsrl_detach(device_t dev) 86750703Swpaul{ 86850703Swpaul struct rl_softc *sc; 86950703Swpaul struct ifnet *ifp; 87050703Swpaul 87150703Swpaul sc = device_get_softc(dev); 872147256Sbrooks ifp = sc->rl_ifp; 873131605Sbms 874112880Sjhb KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 875150720Sjhb 876150789Sglebius#ifdef DEVICE_POLLING 877150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 878150789Sglebius ether_poll_deregister(ifp); 879150789Sglebius#endif 880133403Sgreen /* These should only be active if attach succeeded */ 881150213Sru if (device_is_attached(dev)) { 882150126Sru RL_LOCK(sc); 883150126Sru rl_stop(sc); 884150126Sru RL_UNLOCK(sc); 885150720Sjhb callout_drain(&sc->rl_stat_callout); 886133403Sgreen ether_ifdetach(ifp); 887147256Sbrooks } 888131606Sbms#if 0 889131606Sbms sc->suspended = 1; 890131606Sbms#endif 891113609Snjl if (sc->rl_miibus) 892112872Snjl device_delete_child(dev, sc->rl_miibus); 893113609Snjl bus_generic_detach(dev); 89450703Swpaul 895171560Syongari if (sc->rl_intrhand[0]) 896171560Syongari bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 897171560Syongari if (sc->rl_irq[0]) 898171560Syongari bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]); 899112872Snjl if (sc->rl_res) 900211648Syongari bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 901211648Syongari sc->rl_res); 90250703Swpaul 903151297Sru if (ifp) 904151297Sru if_free(ifp); 905151297Sru 906184240Syongari rl_dma_free(sc); 90750703Swpaul 90867087Swpaul mtx_destroy(&sc->rl_mtx); 90950703Swpaul 910131605Sbms return (0); 91150703Swpaul} 91250703Swpaul 913184240Syongaristatic int 914184240Syongarirl_dma_alloc(struct rl_softc *sc) 915184240Syongari{ 916184240Syongari struct rl_dmamap_arg ctx; 917184240Syongari int error, i; 918184240Syongari 919184240Syongari /* 920184240Syongari * Allocate the parent bus DMA tag appropriate for PCI. 921184240Syongari */ 922184240Syongari error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */ 923184240Syongari 1, 0, /* alignment, boundary */ 924184240Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 925184240Syongari BUS_SPACE_MAXADDR, /* highaddr */ 926184240Syongari NULL, NULL, /* filter, filterarg */ 927184240Syongari BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 928184240Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 929184240Syongari 0, /* flags */ 930184240Syongari NULL, NULL, /* lockfunc, lockarg */ 931184240Syongari &sc->rl_parent_tag); 932184240Syongari if (error) { 933184240Syongari device_printf(sc->rl_dev, 934184240Syongari "failed to create parent DMA tag.\n"); 935184240Syongari goto fail; 936184240Syongari } 937184240Syongari /* Create DMA tag for Rx memory block. */ 938184240Syongari error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 939184240Syongari RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */ 940184240Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 941184240Syongari BUS_SPACE_MAXADDR, /* highaddr */ 942184240Syongari NULL, NULL, /* filter, filterarg */ 943184240Syongari RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */ 944184240Syongari RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */ 945184240Syongari 0, /* flags */ 946184240Syongari NULL, NULL, /* lockfunc, lockarg */ 947184240Syongari &sc->rl_cdata.rl_rx_tag); 948184240Syongari if (error) { 949184240Syongari device_printf(sc->rl_dev, 950184240Syongari "failed to create Rx memory block DMA tag.\n"); 951184240Syongari goto fail; 952184240Syongari } 953184240Syongari /* Create DMA tag for Tx buffer. */ 954184240Syongari error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 955184240Syongari RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */ 956184240Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 957184240Syongari BUS_SPACE_MAXADDR, /* highaddr */ 958184240Syongari NULL, NULL, /* filter, filterarg */ 959184240Syongari MCLBYTES, 1, /* maxsize, nsegments */ 960184240Syongari MCLBYTES, /* maxsegsize */ 961184240Syongari 0, /* flags */ 962184240Syongari NULL, NULL, /* lockfunc, lockarg */ 963184240Syongari &sc->rl_cdata.rl_tx_tag); 964184240Syongari if (error) { 965184240Syongari device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n"); 966184240Syongari goto fail; 967184240Syongari } 968184240Syongari 969184240Syongari /* 970184240Syongari * Allocate DMA'able memory and load DMA map for Rx memory block. 971184240Syongari */ 972184240Syongari error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag, 973184240Syongari (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK | 974184240Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap); 975184240Syongari if (error != 0) { 976184240Syongari device_printf(sc->rl_dev, 977184240Syongari "failed to allocate Rx DMA memory block.\n"); 978184240Syongari goto fail; 979184240Syongari } 980184240Syongari ctx.rl_busaddr = 0; 981184240Syongari error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag, 982184240Syongari sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf, 983184240Syongari RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx, 984184240Syongari BUS_DMA_NOWAIT); 985184240Syongari if (error != 0 || ctx.rl_busaddr == 0) { 986184240Syongari device_printf(sc->rl_dev, 987184240Syongari "could not load Rx DMA memory block.\n"); 988184240Syongari goto fail; 989184240Syongari } 990184240Syongari sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr; 991184240Syongari 992184240Syongari /* Create DMA maps for Tx buffers. */ 993184240Syongari for (i = 0; i < RL_TX_LIST_CNT; i++) { 994184240Syongari sc->rl_cdata.rl_tx_chain[i] = NULL; 995184240Syongari sc->rl_cdata.rl_tx_dmamap[i] = NULL; 996184240Syongari error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0, 997184240Syongari &sc->rl_cdata.rl_tx_dmamap[i]); 998184240Syongari if (error != 0) { 999184240Syongari device_printf(sc->rl_dev, 1000184240Syongari "could not create Tx dmamap.\n"); 1001184240Syongari goto fail; 1002184240Syongari } 1003184240Syongari } 1004184240Syongari 1005184240Syongari /* Leave a few bytes before the start of the RX ring buffer. */ 1006184240Syongari sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1007184240Syongari sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE; 1008184240Syongari 1009184240Syongarifail: 1010184240Syongari return (error); 1011184240Syongari} 1012184240Syongari 1013184240Syongaristatic void 1014184240Syongarirl_dma_free(struct rl_softc *sc) 1015184240Syongari{ 1016184240Syongari int i; 1017184240Syongari 1018184240Syongari /* Rx memory block. */ 1019184240Syongari if (sc->rl_cdata.rl_rx_tag != NULL) { 1020184240Syongari if (sc->rl_cdata.rl_rx_dmamap != NULL) 1021184240Syongari bus_dmamap_unload(sc->rl_cdata.rl_rx_tag, 1022184240Syongari sc->rl_cdata.rl_rx_dmamap); 1023184240Syongari if (sc->rl_cdata.rl_rx_dmamap != NULL && 1024184240Syongari sc->rl_cdata.rl_rx_buf_ptr != NULL) 1025184240Syongari bus_dmamem_free(sc->rl_cdata.rl_rx_tag, 1026184240Syongari sc->rl_cdata.rl_rx_buf_ptr, 1027184240Syongari sc->rl_cdata.rl_rx_dmamap); 1028184240Syongari sc->rl_cdata.rl_rx_buf_ptr = NULL; 1029184240Syongari sc->rl_cdata.rl_rx_buf = NULL; 1030184240Syongari sc->rl_cdata.rl_rx_dmamap = NULL; 1031184240Syongari bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag); 1032184240Syongari sc->rl_cdata.rl_tx_tag = NULL; 1033184240Syongari } 1034184240Syongari 1035184240Syongari /* Tx buffers. */ 1036184240Syongari if (sc->rl_cdata.rl_tx_tag != NULL) { 1037184240Syongari for (i = 0; i < RL_TX_LIST_CNT; i++) { 1038184240Syongari if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) { 1039184240Syongari bus_dmamap_destroy( 1040184240Syongari sc->rl_cdata.rl_tx_tag, 1041184240Syongari sc->rl_cdata.rl_tx_dmamap[i]); 1042184240Syongari sc->rl_cdata.rl_tx_dmamap[i] = NULL; 1043184240Syongari } 1044188392Sfjoe } 1045184240Syongari bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1046184240Syongari sc->rl_cdata.rl_tx_tag = NULL; 1047184240Syongari } 1048184240Syongari 1049184240Syongari if (sc->rl_parent_tag != NULL) { 1050184240Syongari bus_dma_tag_destroy(sc->rl_parent_tag); 1051184240Syongari sc->rl_parent_tag = NULL; 1052184240Syongari } 1053184240Syongari} 1054184240Syongari 105540516Swpaul/* 105640516Swpaul * Initialize the transmit descriptors. 105740516Swpaul */ 1058102335Salfredstatic int 1059131605Sbmsrl_list_tx_init(struct rl_softc *sc) 106040516Swpaul{ 106140516Swpaul struct rl_chain_data *cd; 106240516Swpaul int i; 106340516Swpaul 1064131606Sbms RL_LOCK_ASSERT(sc); 1065131606Sbms 106640516Swpaul cd = &sc->rl_cdata; 106740516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 106845633Swpaul cd->rl_tx_chain[i] = NULL; 106948028Swpaul CSR_WRITE_4(sc, 1070131605Sbms RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 107140516Swpaul } 107240516Swpaul 107345633Swpaul sc->rl_cdata.cur_tx = 0; 107445633Swpaul sc->rl_cdata.last_tx = 0; 107540516Swpaul 1076131605Sbms return (0); 107740516Swpaul} 107840516Swpaul 1079184240Syongaristatic int 1080184240Syongarirl_list_rx_init(struct rl_softc *sc) 1081184240Syongari{ 1082184240Syongari 1083184240Syongari RL_LOCK_ASSERT(sc); 1084184240Syongari 1085184240Syongari bzero(sc->rl_cdata.rl_rx_buf_ptr, 1086184240Syongari RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ); 1087184240Syongari bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap, 1088184240Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1089184240Syongari 1090184240Syongari return (0); 1091184240Syongari} 1092184240Syongari 109340516Swpaul/* 109440516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 109540516Swpaul * the higher level protocols. 109640516Swpaul * 109740516Swpaul * You know there's something wrong with a PCI bus-master chip design 109840516Swpaul * when you have to use m_devget(). 109940516Swpaul * 110040516Swpaul * The receive operation is badly documented in the datasheet, so I'll 110140516Swpaul * attempt to document it here. The driver provides a buffer area and 110240516Swpaul * places its base address in the RX buffer start address register. 110340516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 110472645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 110540516Swpaul * of the frame and certain other status bits. Each frame (starting with 110640516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 110740516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 110840516Swpaul * the 'rx status register' mentioned in the datasheet. 110948028Swpaul * 111048028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 111178508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1112109109Sdes * as the offset argument to m_devget(). 111340516Swpaul */ 1114193096Sattiliostatic int 1115131605Sbmsrl_rxeof(struct rl_softc *sc) 111640516Swpaul{ 1117109109Sdes struct mbuf *m; 1118147256Sbrooks struct ifnet *ifp = sc->rl_ifp; 1119131605Sbms uint8_t *rxbufpos; 112040516Swpaul int total_len = 0; 112140516Swpaul int wrap = 0; 1122193096Sattilio int rx_npkts = 0; 1123131605Sbms uint32_t rxstat; 1124131605Sbms uint16_t cur_rx; 1125131605Sbms uint16_t limit; 1126131605Sbms uint16_t max_bytes, rx_bytes = 0; 112740516Swpaul 1128122689Ssam RL_LOCK_ASSERT(sc); 1129122689Ssam 1130184240Syongari bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap, 1131184240Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 113281713Swpaul 113340516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 113440516Swpaul 113540516Swpaul /* Do not try to read past this point. */ 113640516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 113740516Swpaul 113840516Swpaul if (limit < cur_rx) 113940516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 114040516Swpaul else 114140516Swpaul max_bytes = limit - cur_rx; 114240516Swpaul 114342738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 114494883Sluigi#ifdef DEVICE_POLLING 1145150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 114694883Sluigi if (sc->rxcycles <= 0) 114794883Sluigi break; 114894883Sluigi sc->rxcycles--; 114994883Sluigi } 1150150789Sglebius#endif 115140516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1152131605Sbms rxstat = le32toh(*(uint32_t *)rxbufpos); 115340516Swpaul 115440516Swpaul /* 115540516Swpaul * Here's a totally undocumented fact for you. When the 115640516Swpaul * RealTek chip is in the process of copying a packet into 115740516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 115840516Swpaul * packet header with this value, you need to stop. The 115940516Swpaul * datasheet makes absolutely no mention of this and 116040516Swpaul * RealTek should be shot for this. 116140516Swpaul */ 1162178054Syongari total_len = rxstat >> 16; 1163178054Syongari if (total_len == RL_RXSTAT_UNFINISHED) 116440516Swpaul break; 1165109109Sdes 1166178054Syongari if (!(rxstat & RL_RXSTAT_RXOK) || 1167178054Syongari total_len < ETHER_MIN_LEN || 1168178054Syongari total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 116940516Swpaul ifp->if_ierrors++; 1170211767Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1171131841Sbms rl_init_locked(sc); 1172193096Sattilio return (rx_npkts); 117340516Swpaul } 117440516Swpaul 1175109109Sdes /* No errors; receive the packet. */ 117640516Swpaul rx_bytes += total_len + 4; 117740516Swpaul 117840516Swpaul /* 117942051Swpaul * XXX The RealTek chip includes the CRC with every 118042051Swpaul * received frame, and there's no way to turn this 118142051Swpaul * behavior off (at least, I can't find anything in 1182109109Sdes * the manual that explains how to do it) so we have 118342051Swpaul * to trim off the CRC manually. 118442051Swpaul */ 118542051Swpaul total_len -= ETHER_CRC_LEN; 118642051Swpaul 118742051Swpaul /* 118840516Swpaul * Avoid trying to read more bytes than we know 118940516Swpaul * the chip has prepared for us. 119040516Swpaul */ 119140516Swpaul if (rx_bytes > max_bytes) 119240516Swpaul break; 119340516Swpaul 119440516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 1195131605Sbms ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 119640516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 119740516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 119840516Swpaul 119940516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 120040516Swpaul if (total_len > wrap) { 120178508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 120278508Sbmilekic NULL); 1203185575Syongari if (m != NULL) 120440516Swpaul m_copyback(m, wrap, total_len - wrap, 120540516Swpaul sc->rl_cdata.rl_rx_buf); 120642051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 120740516Swpaul } else { 120878508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 120978508Sbmilekic NULL); 121042051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 121140516Swpaul } 121240516Swpaul 1213131605Sbms /* Round up to 32-bit boundary. */ 121440516Swpaul cur_rx = (cur_rx + 3) & ~3; 121540516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 121640516Swpaul 1217185575Syongari if (m == NULL) { 1218185575Syongari ifp->if_iqdrops++; 121940516Swpaul continue; 1220185575Syongari } 122140516Swpaul 122240516Swpaul ifp->if_ipackets++; 1223122689Ssam RL_UNLOCK(sc); 1224106936Ssam (*ifp->if_input)(ifp, m); 1225122689Ssam RL_LOCK(sc); 1226193096Sattilio rx_npkts++; 122740516Swpaul } 1228184240Syongari 1229184524Simp /* No need to sync Rx memory block as we didn't modify it. */ 1230193096Sattilio return (rx_npkts); 123140516Swpaul} 123240516Swpaul 123340516Swpaul/* 123440516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 123540516Swpaul * the list buffers. 123640516Swpaul */ 1237102335Salfredstatic void 1238131605Sbmsrl_txeof(struct rl_softc *sc) 123940516Swpaul{ 1240147256Sbrooks struct ifnet *ifp = sc->rl_ifp; 1241131605Sbms uint32_t txstat; 124240516Swpaul 1243131606Sbms RL_LOCK_ASSERT(sc); 1244131606Sbms 124540516Swpaul /* 124640516Swpaul * Go through our tx list and free mbufs for those 124740516Swpaul * frames that have been uploaded. 124840516Swpaul */ 124945633Swpaul do { 1250127783Sru if (RL_LAST_TXMBUF(sc) == NULL) 1251127783Sru break; 125245633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 125345633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 125445633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 125540516Swpaul break; 125640516Swpaul 125745633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 125840516Swpaul 1259184240Syongari bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc), 1260184240Syongari BUS_DMASYNC_POSTWRITE); 1261184240Syongari bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc)); 1262127783Sru m_freem(RL_LAST_TXMBUF(sc)); 1263127783Sru RL_LAST_TXMBUF(sc) = NULL; 1264141676Smlaier /* 1265141676Smlaier * If there was a transmit underrun, bump the TX threshold. 1266141676Smlaier * Make sure not to overflow the 63 * 32byte we can address 1267141676Smlaier * with the 6 available bit. 1268141676Smlaier */ 1269141676Smlaier if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 1270141676Smlaier (sc->rl_txthresh < 2016)) 1271141676Smlaier sc->rl_txthresh += 32; 127245633Swpaul if (txstat & RL_TXSTAT_TX_OK) 127345633Swpaul ifp->if_opackets++; 127445633Swpaul else { 127552426Swpaul int oldthresh; 127645633Swpaul ifp->if_oerrors++; 127745633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 127845633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 127945633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 128052426Swpaul oldthresh = sc->rl_txthresh; 128152426Swpaul /* error recovery */ 1282211767Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1283131841Sbms rl_init_locked(sc); 1284141676Smlaier /* restore original threshold */ 1285141676Smlaier sc->rl_txthresh = oldthresh; 128652426Swpaul return; 128745633Swpaul } 128845633Swpaul RL_INC(sc->rl_cdata.last_tx); 1289148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 129045633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 129140516Swpaul 1292127783Sru if (RL_LAST_TXMBUF(sc) == NULL) 1293164811Sru sc->rl_watchdog_timer = 0; 129450703Swpaul} 129540516Swpaul 1296102335Salfredstatic void 1297184515Simprl_twister_update(struct rl_softc *sc) 1298184515Simp{ 1299184515Simp uint16_t linktest; 1300184515Simp /* 1301184515Simp * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for 1302184515Simp * Linux driver. Values undocumented otherwise. 1303184515Simp */ 1304184515Simp static const uint32_t param[4][4] = { 1305184515Simp {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1306184515Simp {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1307184515Simp {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1308184515Simp {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1309184515Simp }; 1310184515Simp 1311184515Simp /* 1312184515Simp * Tune the so-called twister registers of the RTL8139. These 1313184524Simp * are used to compensate for impedance mismatches. The 1314184524Simp * method for tuning these registers is undocumented and the 1315184524Simp * following procedure is collected from public sources. 1316184515Simp */ 1317184515Simp switch (sc->rl_twister) 1318184515Simp { 1319184515Simp case CHK_LINK: 1320184515Simp /* 1321184524Simp * If we have a sufficient link, then we can proceed in 1322184515Simp * the state machine to the next stage. If not, then 1323184515Simp * disable further tuning after writing sane defaults. 1324184515Simp */ 1325184515Simp if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) { 1326184515Simp CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD); 1327184515Simp sc->rl_twister = FIND_ROW; 1328184515Simp } else { 1329184515Simp CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD); 1330184515Simp CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); 1331184515Simp CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); 1332184515Simp CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); 1333184515Simp sc->rl_twister = DONE; 1334184515Simp } 1335184515Simp break; 1336184515Simp case FIND_ROW: 1337184515Simp /* 1338184515Simp * Read how long it took to see the echo to find the tuning 1339184515Simp * row to use. 1340184515Simp */ 1341184515Simp linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; 1342184515Simp if (linktest == RL_CSCFG_ROW3) 1343184515Simp sc->rl_twist_row = 3; 1344184515Simp else if (linktest == RL_CSCFG_ROW2) 1345184515Simp sc->rl_twist_row = 2; 1346184515Simp else if (linktest == RL_CSCFG_ROW1) 1347184515Simp sc->rl_twist_row = 1; 1348184515Simp else 1349184515Simp sc->rl_twist_row = 0; 1350184515Simp sc->rl_twist_col = 0; 1351184515Simp sc->rl_twister = SET_PARAM; 1352184515Simp break; 1353184515Simp case SET_PARAM: 1354184515Simp if (sc->rl_twist_col == 0) 1355184515Simp CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); 1356184515Simp CSR_WRITE_4(sc, RL_PARA7C, 1357184515Simp param[sc->rl_twist_row][sc->rl_twist_col]); 1358184515Simp if (++sc->rl_twist_col == 4) { 1359184515Simp if (sc->rl_twist_row == 3) 1360184515Simp sc->rl_twister = RECHK_LONG; 1361184515Simp else 1362184515Simp sc->rl_twister = DONE; 1363184515Simp } 1364184515Simp break; 1365184515Simp case RECHK_LONG: 1366184515Simp /* 1367184515Simp * For long cables, we have to double check to make sure we 1368184515Simp * don't mistune. 1369184515Simp */ 1370184515Simp linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; 1371184515Simp if (linktest == RL_CSCFG_ROW3) 1372184515Simp sc->rl_twister = DONE; 1373184515Simp else { 1374184515Simp CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE); 1375184515Simp sc->rl_twister = RETUNE; 1376184515Simp } 1377184515Simp break; 1378184515Simp case RETUNE: 1379184515Simp /* Retune for a shorter cable (try column 2) */ 1380184515Simp CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); 1381184515Simp CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); 1382184515Simp CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); 1383184515Simp CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); 1384184515Simp sc->rl_twist_row--; 1385184515Simp sc->rl_twist_col = 0; 1386184515Simp sc->rl_twister = SET_PARAM; 1387184515Simp break; 1388184515Simp 1389184515Simp case DONE: 1390184515Simp break; 1391184515Simp } 1392184515Simp 1393184515Simp} 1394184515Simp 1395184515Simpstatic void 1396131605Sbmsrl_tick(void *xsc) 139750703Swpaul{ 1398131605Sbms struct rl_softc *sc = xsc; 139950703Swpaul struct mii_data *mii; 1400184515Simp int ticks; 140150703Swpaul 1402150720Sjhb RL_LOCK_ASSERT(sc); 1403184515Simp /* 1404184515Simp * If we're doing the twister cable calibration, then we need to defer 1405184515Simp * watchdog timeouts. This is a no-op in normal operations, but 1406184515Simp * can falsely trigger when the cable calibration takes a while and 1407184515Simp * there was traffic ready to go when rl was started. 1408184515Simp * 1409184515Simp * We don't defer mii_tick since that updates the mii status, which 1410184515Simp * helps the twister process, at least according to similar patches 1411184515Simp * for the Linux driver I found online while doing the fixes. Worst 1412184515Simp * case is a few extra mii reads during calibration. 1413184515Simp */ 141450703Swpaul mii = device_get_softc(sc->rl_miibus); 141550703Swpaul mii_tick(mii); 1416186390Syongari if ((sc->rl_flags & RL_FLAG_LINK) == 0) 1417186390Syongari rl_miibus_statchg(sc->rl_dev); 1418184559Simp if (sc->rl_twister_enable) { 1419184559Simp if (sc->rl_twister == DONE) 1420184559Simp rl_watchdog(sc); 1421184559Simp else 1422184559Simp rl_twister_update(sc); 1423184559Simp if (sc->rl_twister == DONE) 1424184559Simp ticks = hz; 1425184559Simp else 1426184559Simp ticks = hz / 10; 1427184559Simp } else { 1428184515Simp rl_watchdog(sc); 1429184515Simp ticks = hz; 1430184559Simp } 1431164811Sru 1432184515Simp callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc); 143340516Swpaul} 143440516Swpaul 143594883Sluigi#ifdef DEVICE_POLLING 1436193096Sattiliostatic int 1437131841Sbmsrl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 143894883Sluigi{ 143994883Sluigi struct rl_softc *sc = ifp->if_softc; 1440193096Sattilio int rx_npkts = 0; 144194883Sluigi 144294883Sluigi RL_LOCK(sc); 1443150789Sglebius if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1444193096Sattilio rx_npkts = rl_poll_locked(ifp, cmd, count); 1445131841Sbms RL_UNLOCK(sc); 1446193096Sattilio return (rx_npkts); 1447131841Sbms} 1448131605Sbms 1449193096Sattiliostatic int 1450131841Sbmsrl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1451131841Sbms{ 1452131841Sbms struct rl_softc *sc = ifp->if_softc; 1453193096Sattilio int rx_npkts; 1454131841Sbms 1455131841Sbms RL_LOCK_ASSERT(sc); 1456131841Sbms 145794883Sluigi sc->rxcycles = count; 1458193096Sattilio rx_npkts = rl_rxeof(sc); 1459119868Swpaul rl_txeof(sc); 1460131605Sbms 1461131841Sbms if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1462131841Sbms rl_start_locked(ifp); 146394883Sluigi 1464131605Sbms if (cmd == POLL_AND_CHECK_STATUS) { 1465131605Sbms uint16_t status; 146694883Sluigi 1467131605Sbms /* We should also check the status register. */ 146894883Sluigi status = CSR_READ_2(sc, RL_ISR); 1469100957Sjhb if (status == 0xffff) 1470193096Sattilio return (rx_npkts); 1471131605Sbms if (status != 0) 147294883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 147394883Sluigi 1474131605Sbms /* XXX We should check behaviour on receiver stalls. */ 147594883Sluigi 1476211767Syongari if (status & RL_ISR_SYSTEM_ERR) { 1477211767Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1478131841Sbms rl_init_locked(sc); 1479211767Syongari } 148094883Sluigi } 1481193096Sattilio return (rx_npkts); 148294883Sluigi} 148394883Sluigi#endif /* DEVICE_POLLING */ 148494883Sluigi 1485102335Salfredstatic void 1486131605Sbmsrl_intr(void *arg) 148740516Swpaul{ 1488131605Sbms struct rl_softc *sc = arg; 1489147256Sbrooks struct ifnet *ifp = sc->rl_ifp; 1490131605Sbms uint16_t status; 1491213796Syongari int count; 149240516Swpaul 1493131606Sbms RL_LOCK(sc); 1494131606Sbms 1495131841Sbms if (sc->suspended) 1496131841Sbms goto done_locked; 149786822Siwasaki 149894883Sluigi#ifdef DEVICE_POLLING 1499150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 1500131841Sbms goto done_locked; 1501150789Sglebius#endif 1502131841Sbms 1503213796Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1504213796Syongari goto done_locked2; 1505213796Syongari status = CSR_READ_2(sc, RL_ISR); 1506213796Syongari if (status == 0xffff || (status & RL_INTRS) == 0) 1507213796Syongari goto done_locked; 1508213796Syongari /* 1509213796Syongari * Ours, disable further interrupts. 1510213796Syongari */ 1511213796Syongari CSR_WRITE_2(sc, RL_IMR, 0); 1512213796Syongari for (count = 16; count > 0; count--) { 1513213796Syongari CSR_WRITE_2(sc, RL_ISR, status); 1514213796Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1515213796Syongari if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR)) 1516213796Syongari rl_rxeof(sc); 1517213796Syongari if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR)) 1518213796Syongari rl_txeof(sc); 1519213796Syongari if (status & RL_ISR_SYSTEM_ERR) { 1520213796Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1521213796Syongari rl_init_locked(sc); 1522213796Syongari RL_UNLOCK(sc); 1523213796Syongari return; 1524213796Syongari } 1525213796Syongari } 152640516Swpaul status = CSR_READ_2(sc, RL_ISR); 1527131605Sbms /* If the card has gone away, the read returns 0xffff. */ 1528213796Syongari if (status == 0xffff || (status & RL_INTRS) == 0) 1529100957Sjhb break; 153040516Swpaul } 153140516Swpaul 1532131841Sbms if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1533131841Sbms rl_start_locked(ifp); 1534131841Sbms 1535213796Syongaridone_locked2: 1536213796Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1537213796Syongari CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1538131841Sbmsdone_locked: 1539131606Sbms RL_UNLOCK(sc); 154040516Swpaul} 154140516Swpaul 154240516Swpaul/* 154340516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 154440516Swpaul * pointers to the fragment pointers. 154540516Swpaul */ 1546102335Salfredstatic int 1547184240Syongarirl_encap(struct rl_softc *sc, struct mbuf **m_head) 154840516Swpaul{ 1549184240Syongari struct mbuf *m; 1550184240Syongari bus_dma_segment_t txsegs[1]; 1551184240Syongari int error, nsegs, padlen; 155240516Swpaul 1553131606Sbms RL_LOCK_ASSERT(sc); 1554131606Sbms 1555184240Syongari m = *m_head; 1556184240Syongari padlen = 0; 155740516Swpaul /* 1558184240Syongari * Hardware doesn't auto-pad, so we have to make sure 1559184240Syongari * pad short frames out to the minimum frame length. 1560184240Syongari */ 1561184240Syongari if (m->m_pkthdr.len < RL_MIN_FRAMELEN) 1562184240Syongari padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len; 1563184240Syongari /* 156445633Swpaul * The RealTek is brain damaged and wants longword-aligned 156545633Swpaul * TX buffers, plus we can only have one fragment buffer 156645633Swpaul * per packet. We have to copy pretty much all the time. 156740516Swpaul */ 1568184240Syongari if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 || 1569184240Syongari (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) { 1570184240Syongari m = m_defrag(*m_head, M_DONTWAIT); 1571184240Syongari if (m == NULL) { 1572184240Syongari m_freem(*m_head); 1573184240Syongari *m_head = NULL; 1574184240Syongari return (ENOMEM); 1575184240Syongari } 1576113496Ssilby } 1577184240Syongari *m_head = m; 157840516Swpaul 1579184240Syongari if (padlen > 0) { 158055058Swpaul /* 1581184524Simp * Make security-conscious people happy: zero out the 158255058Swpaul * bytes in the pad area, since we don't know what 158355058Swpaul * this mbuf cluster buffer's previous user might 158455058Swpaul * have left in it. 1585109109Sdes */ 1586184240Syongari bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1587184240Syongari m->m_pkthdr.len += padlen; 1588184240Syongari m->m_len = m->m_pkthdr.len; 158941243Swpaul } 159040516Swpaul 1591184240Syongari error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag, 1592184240Syongari RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0); 1593184240Syongari if (error != 0) 1594184240Syongari return (error); 1595184240Syongari if (nsegs == 0) { 1596184240Syongari m_freem(*m_head); 1597184240Syongari *m_head = NULL; 1598184240Syongari return (EIO); 1599184240Syongari } 160040516Swpaul 1601184240Syongari RL_CUR_TXMBUF(sc) = m; 1602184240Syongari bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc), 1603184240Syongari BUS_DMASYNC_PREWRITE); 1604184240Syongari CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr)); 1605184240Syongari 1606131605Sbms return (0); 160740516Swpaul} 160840516Swpaul 160940516Swpaul/* 161040516Swpaul * Main transmit routine. 161140516Swpaul */ 1612102335Salfredstatic void 1613131605Sbmsrl_start(struct ifnet *ifp) 161440516Swpaul{ 1615131605Sbms struct rl_softc *sc = ifp->if_softc; 161640516Swpaul 161767087Swpaul RL_LOCK(sc); 1618131841Sbms rl_start_locked(ifp); 1619131841Sbms RL_UNLOCK(sc); 1620131841Sbms} 162140516Swpaul 1622131841Sbmsstatic void 1623131841Sbmsrl_start_locked(struct ifnet *ifp) 1624131841Sbms{ 1625131841Sbms struct rl_softc *sc = ifp->if_softc; 1626131841Sbms struct mbuf *m_head = NULL; 1627131841Sbms 1628131841Sbms RL_LOCK_ASSERT(sc); 1629131841Sbms 1630184245Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1631184245Syongari IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 1632184245Syongari return; 1633184245Syongari 1634131605Sbms while (RL_CUR_TXMBUF(sc) == NULL) { 1635131841Sbms 1636131455Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1637131841Sbms 163840516Swpaul if (m_head == NULL) 163940516Swpaul break; 164040516Swpaul 1641184240Syongari if (rl_encap(sc, &m_head)) { 1642184240Syongari if (m_head == NULL) 1643184240Syongari break; 1644184240Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1645184240Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 164658801Swpaul break; 1647184240Syongari } 164840516Swpaul 1649131605Sbms /* Pass a copy of this mbuf chain to the bpf subsystem. */ 1650106936Ssam BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 165151583Swpaul 1652131605Sbms /* Transmit the frame. */ 165345633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 165452426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 165552426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 165645633Swpaul 165745633Swpaul RL_INC(sc->rl_cdata.cur_tx); 1658113237Ssilby 1659131605Sbms /* Set a timeout in case the chip goes out to lunch. */ 1660164811Sru sc->rl_watchdog_timer = 5; 166140516Swpaul } 166240516Swpaul 166340516Swpaul /* 166445633Swpaul * We broke out of the loop because all our TX slots are 166545633Swpaul * full. Mark the NIC as busy until it drains some of the 166645633Swpaul * packets from the queue. 166745633Swpaul */ 166845633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 1669148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1670131841Sbms} 167145633Swpaul 1672131841Sbmsstatic void 1673131841Sbmsrl_init(void *xsc) 1674131841Sbms{ 1675131841Sbms struct rl_softc *sc = xsc; 1676131841Sbms 1677131841Sbms RL_LOCK(sc); 1678131841Sbms rl_init_locked(sc); 167967087Swpaul RL_UNLOCK(sc); 168040516Swpaul} 168140516Swpaul 1682102335Salfredstatic void 1683131841Sbmsrl_init_locked(struct rl_softc *sc) 168440516Swpaul{ 1685147256Sbrooks struct ifnet *ifp = sc->rl_ifp; 168650703Swpaul struct mii_data *mii; 1687165311Syongari uint32_t eaddr[2]; 168840516Swpaul 1689131841Sbms RL_LOCK_ASSERT(sc); 1690131841Sbms 169150703Swpaul mii = device_get_softc(sc->rl_miibus); 169240516Swpaul 1693211767Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1694211767Syongari return; 1695211767Syongari 169640516Swpaul /* 169740516Swpaul * Cancel pending I/O and free all RX/TX buffers. 169840516Swpaul */ 169940516Swpaul rl_stop(sc); 170040516Swpaul 1701184242Syongari rl_reset(sc); 1702184559Simp if (sc->rl_twister_enable) { 1703184559Simp /* 1704184559Simp * Reset twister register tuning state. The twister 1705184559Simp * registers and their tuning are undocumented, but 1706184559Simp * are necessary to cope with bad links. rl_twister = 1707184559Simp * DONE here will disable this entirely. 1708184559Simp */ 1709184559Simp sc->rl_twister = CHK_LINK; 1710184559Simp } 1711184242Syongari 1712117029Swpaul /* 1713117029Swpaul * Init our MAC address. Even though the chipset 1714117029Swpaul * documentation doesn't mention it, we need to enter "Config 1715117029Swpaul * register write enable" mode to modify the ID registers. 1716117029Swpaul */ 1717117029Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1718165311Syongari bzero(eaddr, sizeof(eaddr)); 1719165311Syongari bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN); 1720165311Syongari CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]); 1721165311Syongari CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]); 1722117029Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 172340516Swpaul 1724184240Syongari /* Init the RX memory block pointer register. */ 1725184240Syongari CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr + 1726184240Syongari RL_RX_8139_BUF_RESERVE); 1727119868Swpaul /* Init TX descriptors. */ 1728119868Swpaul rl_list_tx_init(sc); 1729184240Syongari /* Init Rx memory block. */ 1730184240Syongari rl_list_rx_init(sc); 173140516Swpaul 173240516Swpaul /* 173340516Swpaul * Enable transmit and receive. 173440516Swpaul */ 173540516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 173640516Swpaul 173740516Swpaul /* 173845633Swpaul * Set the initial TX and RX configuration. 173940516Swpaul */ 174045633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 174140516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 174240516Swpaul 1743213306Syongari /* Set RX filter. */ 1744213306Syongari rl_rxfilter(sc); 174540516Swpaul 174694883Sluigi#ifdef DEVICE_POLLING 1747131605Sbms /* Disable interrupts if we are polling. */ 1748150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 174994883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 1750131605Sbms else 1751150789Sglebius#endif 1752131605Sbms /* Enable interrupts. */ 1753119868Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 175440516Swpaul 175552426Swpaul /* Set initial TX threshold */ 175652426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 175752426Swpaul 175840516Swpaul /* Start RX/TX process. */ 175940516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1760119868Swpaul 176140516Swpaul /* Enable receiver and transmitter. */ 176240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 176340516Swpaul 1764184245Syongari sc->rl_flags &= ~RL_FLAG_LINK; 176550703Swpaul mii_mediachg(mii); 176640516Swpaul 1767233489Syongari CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 176840516Swpaul 1769148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 1770148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 177140516Swpaul 1772150720Sjhb callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 177340516Swpaul} 177440516Swpaul 177540516Swpaul/* 177640516Swpaul * Set media options. 177740516Swpaul */ 1778102335Salfredstatic int 1779131605Sbmsrl_ifmedia_upd(struct ifnet *ifp) 178040516Swpaul{ 1781131605Sbms struct rl_softc *sc = ifp->if_softc; 178250703Swpaul struct mii_data *mii; 178340516Swpaul 178450703Swpaul mii = device_get_softc(sc->rl_miibus); 1785131605Sbms 1786150720Sjhb RL_LOCK(sc); 178750703Swpaul mii_mediachg(mii); 1788150720Sjhb RL_UNLOCK(sc); 178940516Swpaul 1790131605Sbms return (0); 179140516Swpaul} 179240516Swpaul 179340516Swpaul/* 179440516Swpaul * Report current media status. 179540516Swpaul */ 1796102335Salfredstatic void 1797131605Sbmsrl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 179840516Swpaul{ 1799131605Sbms struct rl_softc *sc = ifp->if_softc; 180050703Swpaul struct mii_data *mii; 180140516Swpaul 180250703Swpaul mii = device_get_softc(sc->rl_miibus); 180340516Swpaul 1804150720Sjhb RL_LOCK(sc); 180550703Swpaul mii_pollstat(mii); 180650703Swpaul ifmr->ifm_active = mii->mii_media_active; 180750703Swpaul ifmr->ifm_status = mii->mii_media_status; 1808229057Syongari RL_UNLOCK(sc); 180940516Swpaul} 181040516Swpaul 1811102335Salfredstatic int 1812131605Sbmsrl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 181340516Swpaul{ 1814131605Sbms struct ifreq *ifr = (struct ifreq *)data; 1815131605Sbms struct mii_data *mii; 181640516Swpaul struct rl_softc *sc = ifp->if_softc; 1817210244Syongari int error = 0, mask; 181840516Swpaul 1819131605Sbms switch (command) { 182040516Swpaul case SIOCSIFFLAGS: 1821131841Sbms RL_LOCK(sc); 182240516Swpaul if (ifp->if_flags & IFF_UP) { 1823213306Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1824213306Syongari ((ifp->if_flags ^ sc->rl_if_flags) & 1825213306Syongari (IFF_PROMISC | IFF_ALLMULTI))) 1826213306Syongari rl_rxfilter(sc); 1827213306Syongari else 1828213306Syongari rl_init_locked(sc); 1829213306Syongari } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1830213306Syongari rl_stop(sc); 1831213306Syongari sc->rl_if_flags = ifp->if_flags; 1832131841Sbms RL_UNLOCK(sc); 183340516Swpaul break; 183440516Swpaul case SIOCADDMULTI: 183540516Swpaul case SIOCDELMULTI: 1836131606Sbms RL_LOCK(sc); 1837213306Syongari rl_rxfilter(sc); 1838131606Sbms RL_UNLOCK(sc); 183940516Swpaul break; 184040516Swpaul case SIOCGIFMEDIA: 184140516Swpaul case SIOCSIFMEDIA: 184250703Swpaul mii = device_get_softc(sc->rl_miibus); 184350703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 184440516Swpaul break; 1845128121Sru case SIOCSIFCAP: 1846210244Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1847150789Sglebius#ifdef DEVICE_POLLING 1848150789Sglebius if (ifr->ifr_reqcap & IFCAP_POLLING && 1849150789Sglebius !(ifp->if_capenable & IFCAP_POLLING)) { 1850150789Sglebius error = ether_poll_register(rl_poll, ifp); 1851150789Sglebius if (error) 1852150789Sglebius return(error); 1853150789Sglebius RL_LOCK(sc); 1854150789Sglebius /* Disable interrupts */ 1855150789Sglebius CSR_WRITE_2(sc, RL_IMR, 0x0000); 1856150789Sglebius ifp->if_capenable |= IFCAP_POLLING; 1857150789Sglebius RL_UNLOCK(sc); 1858150789Sglebius return (error); 1859150789Sglebius 1860150789Sglebius } 1861150789Sglebius if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1862150789Sglebius ifp->if_capenable & IFCAP_POLLING) { 1863150789Sglebius error = ether_poll_deregister(ifp); 1864150789Sglebius /* Enable interrupts. */ 1865150789Sglebius RL_LOCK(sc); 1866150789Sglebius CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1867150789Sglebius ifp->if_capenable &= ~IFCAP_POLLING; 1868150789Sglebius RL_UNLOCK(sc); 1869150789Sglebius return (error); 1870150789Sglebius } 1871150789Sglebius#endif /* DEVICE_POLLING */ 1872210244Syongari if ((mask & IFCAP_WOL) != 0 && 1873210244Syongari (ifp->if_capabilities & IFCAP_WOL) != 0) { 1874210244Syongari if ((mask & IFCAP_WOL_UCAST) != 0) 1875210244Syongari ifp->if_capenable ^= IFCAP_WOL_UCAST; 1876210244Syongari if ((mask & IFCAP_WOL_MCAST) != 0) 1877210244Syongari ifp->if_capenable ^= IFCAP_WOL_MCAST; 1878210244Syongari if ((mask & IFCAP_WOL_MAGIC) != 0) 1879210244Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1880210244Syongari } 1881128121Sru break; 188240516Swpaul default: 1883106936Ssam error = ether_ioctl(ifp, command, data); 188440516Swpaul break; 188540516Swpaul } 188640516Swpaul 1887131605Sbms return (error); 188840516Swpaul} 188940516Swpaul 1890102335Salfredstatic void 1891164811Srurl_watchdog(struct rl_softc *sc) 189240516Swpaul{ 189340516Swpaul 1894164811Sru RL_LOCK_ASSERT(sc); 1895131605Sbms 1896164811Sru if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0) 1897164811Sru return; 189850703Swpaul 1899164811Sru device_printf(sc->rl_dev, "watchdog timeout\n"); 1900164811Sru sc->rl_ifp->if_oerrors++; 1901164811Sru 1902119868Swpaul rl_txeof(sc); 1903119868Swpaul rl_rxeof(sc); 1904211767Syongari sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1905131841Sbms rl_init_locked(sc); 190640516Swpaul} 190740516Swpaul 190840516Swpaul/* 190940516Swpaul * Stop the adapter and free any mbufs allocated to the 191040516Swpaul * RX and TX lists. 191140516Swpaul */ 1912102335Salfredstatic void 1913131605Sbmsrl_stop(struct rl_softc *sc) 191440516Swpaul{ 191540516Swpaul register int i; 1916147256Sbrooks struct ifnet *ifp = sc->rl_ifp; 191740516Swpaul 1918131606Sbms RL_LOCK_ASSERT(sc); 1919131606Sbms 1920164811Sru sc->rl_watchdog_timer = 0; 1921150720Sjhb callout_stop(&sc->rl_stat_callout); 1922148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1923184245Syongari sc->rl_flags &= ~RL_FLAG_LINK; 192450703Swpaul 192540516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 192640516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 1927184243Syongari for (i = 0; i < RL_TIMEOUT; i++) { 1928184243Syongari DELAY(10); 1929184243Syongari if ((CSR_READ_1(sc, RL_COMMAND) & 1930184243Syongari (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0) 1931184243Syongari break; 1932184243Syongari } 1933184243Syongari if (i == RL_TIMEOUT) 1934184243Syongari device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n"); 193540516Swpaul 1936119868Swpaul /* 1937119868Swpaul * Free the TX list buffers. 1938119868Swpaul */ 1939119868Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 1940119868Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1941184240Syongari if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1942184240Syongari bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, 1943184240Syongari sc->rl_cdata.rl_tx_dmamap[i], 1944184240Syongari BUS_DMASYNC_POSTWRITE); 1945184240Syongari bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, 1946184240Syongari sc->rl_cdata.rl_tx_dmamap[i]); 1947184240Syongari m_freem(sc->rl_cdata.rl_tx_chain[i]); 1948184240Syongari sc->rl_cdata.rl_tx_chain[i] = NULL; 1949184240Syongari } 1950131605Sbms CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1951124816Swpaul 0x0000000); 195240516Swpaul } 195340516Swpaul } 195440516Swpaul} 195540516Swpaul 195640516Swpaul/* 195786822Siwasaki * Device suspend routine. Stop the interface and save some PCI 195886822Siwasaki * settings in case the BIOS doesn't restore them properly on 195986822Siwasaki * resume. 196086822Siwasaki */ 1961102335Salfredstatic int 1962131605Sbmsrl_suspend(device_t dev) 196386822Siwasaki{ 196486822Siwasaki struct rl_softc *sc; 196586822Siwasaki 196686822Siwasaki sc = device_get_softc(dev); 1967131606Sbms 1968131606Sbms RL_LOCK(sc); 196986822Siwasaki rl_stop(sc); 1970210244Syongari rl_setwol(sc); 197186822Siwasaki sc->suspended = 1; 1972131606Sbms RL_UNLOCK(sc); 197386822Siwasaki 197486822Siwasaki return (0); 197586822Siwasaki} 197686822Siwasaki 197786822Siwasaki/* 197886822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 197986822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 198086822Siwasaki * appropriate. 198186822Siwasaki */ 1982102335Salfredstatic int 1983131605Sbmsrl_resume(device_t dev) 198486822Siwasaki{ 198586822Siwasaki struct rl_softc *sc; 198686822Siwasaki struct ifnet *ifp; 1987210244Syongari int pmc; 1988210244Syongari uint16_t pmstat; 198986822Siwasaki 199086822Siwasaki sc = device_get_softc(dev); 1991147256Sbrooks ifp = sc->rl_ifp; 199286822Siwasaki 1993131841Sbms RL_LOCK(sc); 1994131841Sbms 1995210244Syongari if ((ifp->if_capabilities & IFCAP_WOL) != 0 && 1996219902Sjhb pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { 1997210244Syongari /* Disable PME and clear PME status. */ 1998210244Syongari pmstat = pci_read_config(sc->rl_dev, 1999210244Syongari pmc + PCIR_POWER_STATUS, 2); 2000210244Syongari if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2001210244Syongari pmstat &= ~PCIM_PSTAT_PMEENABLE; 2002210244Syongari pci_write_config(sc->rl_dev, 2003210244Syongari pmc + PCIR_POWER_STATUS, pmstat, 2); 2004210244Syongari } 2005210244Syongari /* 2006210244Syongari * Clear WOL matching such that normal Rx filtering 2007210244Syongari * wouldn't interfere with WOL patterns. 2008210244Syongari */ 2009210244Syongari rl_clrwol(sc); 2010210244Syongari } 2011210244Syongari 2012109109Sdes /* reinitialize interface if necessary */ 2013109109Sdes if (ifp->if_flags & IFF_UP) 2014131841Sbms rl_init_locked(sc); 201586822Siwasaki 201686822Siwasaki sc->suspended = 0; 2017131841Sbms 2018131606Sbms RL_UNLOCK(sc); 201986822Siwasaki 202086822Siwasaki return (0); 202186822Siwasaki} 202286822Siwasaki 202386822Siwasaki/* 202440516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 202540516Swpaul * get confused by errant DMAs when rebooting. 202640516Swpaul */ 2027173839Syongaristatic int 2028131605Sbmsrl_shutdown(device_t dev) 202940516Swpaul{ 203050703Swpaul struct rl_softc *sc; 203140516Swpaul 203250703Swpaul sc = device_get_softc(dev); 2033131606Sbms 2034131606Sbms RL_LOCK(sc); 203540516Swpaul rl_stop(sc); 2036210244Syongari /* 2037210244Syongari * Mark interface as down since otherwise we will panic if 2038210244Syongari * interrupt comes in later on, which can happen in some 2039210244Syongari * cases. 2040210244Syongari */ 2041210244Syongari sc->rl_ifp->if_flags &= ~IFF_UP; 2042210244Syongari rl_setwol(sc); 2043131606Sbms RL_UNLOCK(sc); 2044173839Syongari 2045173839Syongari return (0); 204640516Swpaul} 2047210244Syongari 2048210244Syongaristatic void 2049210244Syongarirl_setwol(struct rl_softc *sc) 2050210244Syongari{ 2051210244Syongari struct ifnet *ifp; 2052210244Syongari int pmc; 2053210244Syongari uint16_t pmstat; 2054210244Syongari uint8_t v; 2055210244Syongari 2056210244Syongari RL_LOCK_ASSERT(sc); 2057210244Syongari 2058210244Syongari ifp = sc->rl_ifp; 2059210244Syongari if ((ifp->if_capabilities & IFCAP_WOL) == 0) 2060210244Syongari return; 2061219902Sjhb if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2062210244Syongari return; 2063210244Syongari 2064210244Syongari /* Enable config register write. */ 2065210244Syongari CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2066210244Syongari 2067210244Syongari /* Enable PME. */ 2068233489Syongari v = CSR_READ_1(sc, sc->rl_cfg1); 2069210244Syongari v &= ~RL_CFG1_PME; 2070210244Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 2071210244Syongari v |= RL_CFG1_PME; 2072233489Syongari CSR_WRITE_1(sc, sc->rl_cfg1, v); 2073210244Syongari 2074233489Syongari v = CSR_READ_1(sc, sc->rl_cfg3); 2075210244Syongari v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2076210244Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2077210244Syongari v |= RL_CFG3_WOL_MAGIC; 2078233489Syongari CSR_WRITE_1(sc, sc->rl_cfg3, v); 2079210244Syongari 2080233489Syongari v = CSR_READ_1(sc, sc->rl_cfg5); 2081210244Syongari v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2082210244Syongari v &= ~RL_CFG5_WOL_LANWAKE; 2083210244Syongari if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2084210244Syongari v |= RL_CFG5_WOL_UCAST; 2085210244Syongari if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2086210244Syongari v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 2087210244Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 2088210244Syongari v |= RL_CFG5_WOL_LANWAKE; 2089233489Syongari CSR_WRITE_1(sc, sc->rl_cfg5, v); 2090233489Syongari 2091233489Syongari /* Config register write done. */ 2092233489Syongari CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2093233489Syongari 2094210244Syongari /* Request PME if WOL is requested. */ 2095210244Syongari pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 2096210244Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2097210244Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 2098210244Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2099210244Syongari pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2100210244Syongari} 2101210244Syongari 2102210244Syongaristatic void 2103210244Syongarirl_clrwol(struct rl_softc *sc) 2104210244Syongari{ 2105210244Syongari struct ifnet *ifp; 2106210244Syongari uint8_t v; 2107210244Syongari 2108210244Syongari ifp = sc->rl_ifp; 2109210244Syongari if ((ifp->if_capabilities & IFCAP_WOL) == 0) 2110210244Syongari return; 2111210244Syongari 2112210244Syongari /* Enable config register write. */ 2113210244Syongari CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2114210244Syongari 2115233489Syongari v = CSR_READ_1(sc, sc->rl_cfg3); 2116210244Syongari v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2117233489Syongari CSR_WRITE_1(sc, sc->rl_cfg3, v); 2118210244Syongari 2119210244Syongari /* Config register write done. */ 2120210244Syongari CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2121210244Syongari 2122233489Syongari v = CSR_READ_1(sc, sc->rl_cfg5); 2123210244Syongari v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2124210244Syongari v &= ~RL_CFG5_WOL_LANWAKE; 2125233489Syongari CSR_WRITE_1(sc, sc->rl_cfg5, v); 2126210244Syongari} 2127