Searched refs:CSR_READ_4 (Results 1 - 25 of 70) sorted by relevance

123

/freebsd-9.3-release/sys/dev/dc/
H A Ddcphy.c74 CSR_READ_4(sc, reg) | x)
78 CSR_READ_4(sc, reg) & ~x)
207 mode = CSR_READ_4(dc_sc, DC_NETCFG);
262 reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
308 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);
312 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {
365 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)
369 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
H A Dpnphy.c208 reg = CSR_READ_4(dc_sc, DC_ISR);
211 reg = CSR_READ_4(dc_sc, DC_NETCFG);
H A Dif_dc.c362 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
365 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
376 CSR_READ_4(sc, DC_BUSCTL);
412 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
524 r = CSR_READ_4(sc, DC_SIO);
545 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
548 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
586 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
649 val = CSR_READ_4(sc, DC_SIO);
697 rval = CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/et/
H A Dif_et.c435 val = CSR_READ_4(sc, ET_MII_IND);
449 val = CSR_READ_4(sc, ET_MII_STAT);
480 val = CSR_READ_4(sc, ET_MII_IND);
535 ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
537 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
540 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
584 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
657 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~(
1185 status = CSR_READ_4(sc, ET_INTR_STATUS);
1480 if ((CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/bge/
H A Dif_bge.c666 CSR_READ_4(sc, off);
1008 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1016 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1023 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1035 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1044 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1100 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1110 byte = CSR_READ_4(sc, BGE_EE_DATA);
1161 val = CSR_READ_4(sc, BGE_MI_COMM);
1164 val = CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/bfe/
H A Dif_bfe.c671 val = CSR_READ_4(sc, BFE_TX_CTRL);
677 flow = CSR_READ_4(sc, BFE_RXCONF);
687 flow = CSR_READ_4(sc, BFE_MAC_FLOW);
864 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
866 val = CSR_READ_4(sc, BFE_SBINTVEC);
870 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
886 CSR_READ_4(sc, reg);
888 CSR_READ_4(sc, reg);
912 CSR_READ_4(sc, BFE_IMASK);
933 val = CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/vx/
H A Dif_vxvar.h67 #define CSR_READ_4(sc, reg) \ macro
/freebsd-9.3-release/sys/dev/nge/
H A Dif_nge.c247 CSR_READ_4(sc, reg) | (x))
251 CSR_READ_4(sc, reg) & ~(x))
254 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
257 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
265 CSR_READ_4(sc, NGE_CSR);
349 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
389 val = CSR_READ_4(sc, NGE_MEAR);
429 reg = CSR_READ_4(sc, NGE_TBI_BMSR);
455 return (CSR_READ_4(sc, reg));
589 reg = CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/alc/
H A Dif_alc.c251 v = CSR_READ_4(sc, ALC_MDIO);
278 v = CSR_READ_4(sc, ALC_MDIO);
330 reg = CSR_READ_4(sc, ALC_MAC_CFG);
414 opt = CSR_READ_4(sc, ALC_OPT_CFG);
415 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
416 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
428 CSR_READ_4(sc, ALC_OPT_CFG);
453 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
455 CSR_READ_4(sc, ALC_WOL_CFG);
457 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/sis/
H A Dif_sis.c119 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) macro
195 CSR_READ_4(sc, reg) | (x))
199 CSR_READ_4(sc, reg) & ~(x))
202 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
205 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
228 CSR_READ_4(sc, SIS_CSR);
312 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
414 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
415 csrsave = CSR_READ_4(sc, SIS_CSR);
445 val = CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/jme/
H A Dif_jme.c230 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
262 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
359 reg = CSR_READ_4(sc, JME_SMBCSR);
374 reg = CSR_READ_4(sc, JME_SMBINTF);
384 reg = CSR_READ_4(sc, JME_SMBINTF);
492 par0 = CSR_READ_4(sc, JME_PAR0);
493 par1 = CSR_READ_4(sc, JME_PAR1);
711 reg = CSR_READ_4(sc, JME_CHIPMODE);
754 reg = CSR_READ_4(sc, JME_SMBCSR);
770 sc->jme_phyaddr = CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/bwi/
H A Dbwimac.c197 return CSR_READ_4(sc, BWI_MOBJ_DATA);
246 CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */
465 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
471 CSR_READ_4(sc, BWI_STATE_LO);
477 CSR_READ_4(sc, BWI_STATE_LO);
482 status = CSR_READ_4(sc, BWI_MAC_STATUS);
572 val = CSR_READ_4(sc, BWI_MAC_STATUS);
579 val = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
721 CSR_READ_4(sc, BWI_MAC_STATUS); /* dummy read */
1067 intr_status = CSR_READ_4(s
[all...]
H A Dif_bwi.c769 val = CSR_READ_4(sc, BWI_ID_HI);
804 info = CSR_READ_4(sc, BWI_INFO);
809 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
937 val = CSR_READ_4(sc, BWI_FLAGS);
994 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
996 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1083 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1096 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1144 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1267 if ((CSR_READ_4(s
[all...]
H A Dif_bwivar.h75 #define CSR_READ_4(sc, reg) \ macro
86 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
91 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
96 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
/freebsd-9.3-release/sys/dev/vge/
H A Dif_vgevar.h224 #define CSR_READ_4(sc, reg) \ macro
236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
243 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
/freebsd-9.3-release/sys/dev/lge/
H A Dif_lge.c197 CSR_READ_4(sc, reg) | (x))
201 CSR_READ_4(sc, reg) & ~(x))
204 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
225 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
233 val = CSR_READ_4(sc, LGE_EEDATA);
290 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
298 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
315 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
420 if (!(CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/stge/
H A Dif_stge.c517 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
1001 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
1059 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1392 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1398 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1403 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1419 txstat = CSR_READ_4(sc, STGE_TxStatus);
1441 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1877 CSR_READ_4(sc,STGE_OctetRcvOk);
1879 ifp->if_ipackets += CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/wb/
H A Dif_wb.c236 CSR_READ_4(sc, reg) | (x))
240 CSR_READ_4(sc, reg) & ~(x))
244 CSR_READ_4(sc, WB_SIO) | (x))
248 CSR_READ_4(sc, WB_SIO) & ~(x))
307 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
354 val = CSR_READ_4(sc, WB_SIO);
424 rxfilt = CSR_READ_4(sc, WB_NETCFG);
475 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
481 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
482 (CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/arm/xscale/ixp425/
H A Dixp425_pci_space.c64 #define CSR_READ_4(x) *(volatile uint32_t *) \ macro
261 data = CSR_READ_4(PCI_NP_RDATA);
262 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
343 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
/freebsd-9.3-release/sys/dev/age/
H A Dif_age.c221 v = CSR_READ_4(sc, AGE_MDIO);
251 v = CSR_READ_4(sc, AGE_MDIO);
343 reg = CSR_READ_4(sc, AGE_SPI_CTRL);
355 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
359 reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
372 ea[0] = CSR_READ_4(sc, AGE_PAR0);
373 ea[1] = CSR_READ_4(sc, AGE_PAR1);
499 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
523 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
524 CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/ale/
H A Dif_ale.c213 v = CSR_READ_4(sc, ALE_MDIO);
240 v = CSR_READ_4(sc, ALE_MDIO);
290 reg = CSR_READ_4(sc, ALE_MAC_CFG);
363 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
378 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
391 ea[0] = CSR_READ_4(sc, ALE_PAR0);
392 ea[1] = CSR_READ_4(sc, ALE_PAR1);
492 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
518 sc->ale_chip_rev = CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/bm/
H A Dif_bmreg.h162 #define CSR_READ_4(sc, reg) \ macro
/freebsd-9.3-release/sys/dev/tx/
H A Dif_txvar.h136 #define CSR_READ_4(sc, reg) \ macro
/freebsd-9.3-release/sys/dev/my/
H A Dif_my.c141 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
142 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
176 miir = CSR_READ_4(sc, MY_MANAGEMENT);
241 miir = CSR_READ_4(sc, MY_MANAGEMENT);
320 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
722 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
727 if (!(CSR_READ_4(sc, MY_TCRRCR) &
759 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
1213 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1234 if (CSR_READ_4(s
[all...]
/freebsd-9.3-release/sys/dev/tl/
H A Dif_tlreg.h468 #define CSR_READ_4(sc, reg) bus_read_4(sc->tl_res, reg) macro
477 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x))
479 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x))

Completed in 349 milliseconds

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