1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD$"); 36 37/* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72#include <sys/param.h> 73#include <sys/systm.h> 74#include <sys/sockio.h> 75#include <sys/mbuf.h> 76#include <sys/malloc.h> 77#include <sys/kernel.h> 78#include <sys/module.h> 79#include <sys/socket.h> 80 81#include <net/if.h> 82#include <net/if_arp.h> 83#include <net/ethernet.h> 84#include <net/if_dl.h> 85#include <net/if_media.h> 86#include <net/if_types.h> 87 88#include <net/bpf.h> 89 90#include <vm/vm.h> /* for vtophys */ 91#include <vm/pmap.h> /* for vtophys */ 92#include <machine/bus.h> 93#include <machine/resource.h> 94#include <sys/bus.h> 95#include <sys/rman.h> 96 97#include <dev/mii/mii.h> 98#include <dev/mii/miivar.h> 99 100#include <dev/pci/pcireg.h> 101#include <dev/pci/pcivar.h> 102 103#define LGE_USEIOSPACE 104 105#include <dev/lge/if_lgereg.h> 106 107/* "device miibus" required. See GENERIC if you get errors here. */ 108#include "miibus_if.h" 109 110/* 111 * Various supported device vendors/types and their names. 112 */ 113static const struct lge_type lge_devs[] = { 114 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 115 { 0, 0, NULL } 116}; 117 118static int lge_probe(device_t); 119static int lge_attach(device_t); 120static int lge_detach(device_t); 121 122static int lge_alloc_jumbo_mem(struct lge_softc *); 123static void lge_free_jumbo_mem(struct lge_softc *); 124static void *lge_jalloc(struct lge_softc *); 125static void lge_jfree(void *, void *); 126 127static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 128static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 129static void lge_rxeof(struct lge_softc *, int); 130static void lge_rxeoc(struct lge_softc *); 131static void lge_txeof(struct lge_softc *); 132static void lge_intr(void *); 133static void lge_tick(void *); 134static void lge_start(struct ifnet *); 135static void lge_start_locked(struct ifnet *); 136static int lge_ioctl(struct ifnet *, u_long, caddr_t); 137static void lge_init(void *); 138static void lge_init_locked(struct lge_softc *); 139static void lge_stop(struct lge_softc *); 140static void lge_watchdog(struct lge_softc *); 141static int lge_shutdown(device_t); 142static int lge_ifmedia_upd(struct ifnet *); 143static void lge_ifmedia_upd_locked(struct ifnet *); 144static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 145 146static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 147static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 148 149static int lge_miibus_readreg(device_t, int, int); 150static int lge_miibus_writereg(device_t, int, int, int); 151static void lge_miibus_statchg(device_t); 152 153static void lge_setmulti(struct lge_softc *); 154static void lge_reset(struct lge_softc *); 155static int lge_list_rx_init(struct lge_softc *); 156static int lge_list_tx_init(struct lge_softc *); 157 158#ifdef LGE_USEIOSPACE 159#define LGE_RES SYS_RES_IOPORT 160#define LGE_RID LGE_PCI_LOIO 161#else 162#define LGE_RES SYS_RES_MEMORY 163#define LGE_RID LGE_PCI_LOMEM 164#endif 165 166static device_method_t lge_methods[] = { 167 /* Device interface */ 168 DEVMETHOD(device_probe, lge_probe), 169 DEVMETHOD(device_attach, lge_attach), 170 DEVMETHOD(device_detach, lge_detach), 171 DEVMETHOD(device_shutdown, lge_shutdown), 172 173 /* MII interface */ 174 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 175 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 176 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 177 178 DEVMETHOD_END 179}; 180 181static driver_t lge_driver = { 182 "lge", 183 lge_methods, 184 sizeof(struct lge_softc) 185}; 186 187static devclass_t lge_devclass; 188 189DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 190DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 191MODULE_DEPEND(lge, pci, 1, 1, 1); 192MODULE_DEPEND(lge, ether, 1, 1, 1); 193MODULE_DEPEND(lge, miibus, 1, 1, 1); 194 195#define LGE_SETBIT(sc, reg, x) \ 196 CSR_WRITE_4(sc, reg, \ 197 CSR_READ_4(sc, reg) | (x)) 198 199#define LGE_CLRBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, \ 201 CSR_READ_4(sc, reg) & ~(x)) 202 203#define SIO_SET(x) \ 204 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 205 206#define SIO_CLR(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 208 209/* 210 * Read a word of data stored in the EEPROM at address 'addr.' 211 */ 212static void 213lge_eeprom_getword(sc, addr, dest) 214 struct lge_softc *sc; 215 int addr; 216 u_int16_t *dest; 217{ 218 register int i; 219 u_int32_t val; 220 221 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 222 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 223 224 for (i = 0; i < LGE_TIMEOUT; i++) 225 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 226 break; 227 228 if (i == LGE_TIMEOUT) { 229 device_printf(sc->lge_dev, "EEPROM read timed out\n"); 230 return; 231 } 232 233 val = CSR_READ_4(sc, LGE_EEDATA); 234 235 if (addr & 1) 236 *dest = (val >> 16) & 0xFFFF; 237 else 238 *dest = val & 0xFFFF; 239 240 return; 241} 242 243/* 244 * Read a sequence of words from the EEPROM. 245 */ 246static void 247lge_read_eeprom(sc, dest, off, cnt, swap) 248 struct lge_softc *sc; 249 caddr_t dest; 250 int off; 251 int cnt; 252 int swap; 253{ 254 int i; 255 u_int16_t word = 0, *ptr; 256 257 for (i = 0; i < cnt; i++) { 258 lge_eeprom_getword(sc, off + i, &word); 259 ptr = (u_int16_t *)(dest + (i * 2)); 260 if (swap) 261 *ptr = ntohs(word); 262 else 263 *ptr = word; 264 } 265 266 return; 267} 268 269static int 270lge_miibus_readreg(dev, phy, reg) 271 device_t dev; 272 int phy, reg; 273{ 274 struct lge_softc *sc; 275 int i; 276 277 sc = device_get_softc(dev); 278 279 /* 280 * If we have a non-PCS PHY, pretend that the internal 281 * autoneg stuff at PHY address 0 isn't there so that 282 * the miibus code will find only the GMII PHY. 283 */ 284 if (sc->lge_pcs == 0 && phy == 0) 285 return(0); 286 287 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 288 289 for (i = 0; i < LGE_TIMEOUT; i++) 290 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 291 break; 292 293 if (i == LGE_TIMEOUT) { 294 device_printf(sc->lge_dev, "PHY read timed out\n"); 295 return(0); 296 } 297 298 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 299} 300 301static int 302lge_miibus_writereg(dev, phy, reg, data) 303 device_t dev; 304 int phy, reg, data; 305{ 306 struct lge_softc *sc; 307 int i; 308 309 sc = device_get_softc(dev); 310 311 CSR_WRITE_4(sc, LGE_GMIICTL, 312 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 313 314 for (i = 0; i < LGE_TIMEOUT; i++) 315 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 316 break; 317 318 if (i == LGE_TIMEOUT) { 319 device_printf(sc->lge_dev, "PHY write timed out\n"); 320 return(0); 321 } 322 323 return(0); 324} 325 326static void 327lge_miibus_statchg(dev) 328 device_t dev; 329{ 330 struct lge_softc *sc; 331 struct mii_data *mii; 332 333 sc = device_get_softc(dev); 334 mii = device_get_softc(sc->lge_miibus); 335 336 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 337 switch (IFM_SUBTYPE(mii->mii_media_active)) { 338 case IFM_1000_T: 339 case IFM_1000_SX: 340 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 341 break; 342 case IFM_100_TX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 344 break; 345 case IFM_10_T: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 347 break; 348 default: 349 /* 350 * Choose something, even if it's wrong. Clearing 351 * all the bits will hose autoneg on the internal 352 * PHY. 353 */ 354 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 355 break; 356 } 357 358 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 359 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 360 } else { 361 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 362 } 363 364 return; 365} 366 367static void 368lge_setmulti(sc) 369 struct lge_softc *sc; 370{ 371 struct ifnet *ifp; 372 struct ifmultiaddr *ifma; 373 u_int32_t h = 0, hashes[2] = { 0, 0 }; 374 375 ifp = sc->lge_ifp; 376 LGE_LOCK_ASSERT(sc); 377 378 /* Make sure multicast hash table is enabled. */ 379 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 380 381 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 382 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 383 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 384 return; 385 } 386 387 /* first, zot all the existing hash bits */ 388 CSR_WRITE_4(sc, LGE_MAR0, 0); 389 CSR_WRITE_4(sc, LGE_MAR1, 0); 390 391 /* now program new ones */ 392 if_maddr_rlock(ifp); 393 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 394 if (ifma->ifma_addr->sa_family != AF_LINK) 395 continue; 396 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 397 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 398 if (h < 32) 399 hashes[0] |= (1 << h); 400 else 401 hashes[1] |= (1 << (h - 32)); 402 } 403 if_maddr_runlock(ifp); 404 405 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 406 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 407 408 return; 409} 410 411static void 412lge_reset(sc) 413 struct lge_softc *sc; 414{ 415 register int i; 416 417 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 418 419 for (i = 0; i < LGE_TIMEOUT; i++) { 420 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 421 break; 422 } 423 424 if (i == LGE_TIMEOUT) 425 device_printf(sc->lge_dev, "reset never completed\n"); 426 427 /* Wait a little while for the chip to get its brains in order. */ 428 DELAY(1000); 429 430 return; 431} 432 433/* 434 * Probe for a Level 1 chip. Check the PCI vendor and device 435 * IDs against our list and return a device name if we find a match. 436 */ 437static int 438lge_probe(dev) 439 device_t dev; 440{ 441 const struct lge_type *t; 442 443 t = lge_devs; 444 445 while(t->lge_name != NULL) { 446 if ((pci_get_vendor(dev) == t->lge_vid) && 447 (pci_get_device(dev) == t->lge_did)) { 448 device_set_desc(dev, t->lge_name); 449 return(BUS_PROBE_DEFAULT); 450 } 451 t++; 452 } 453 454 return(ENXIO); 455} 456 457/* 458 * Attach the interface. Allocate softc structures, do ifmedia 459 * setup and ethernet/BPF attach. 460 */ 461static int 462lge_attach(dev) 463 device_t dev; 464{ 465 u_char eaddr[ETHER_ADDR_LEN]; 466 struct lge_softc *sc; 467 struct ifnet *ifp = NULL; 468 int error = 0, rid; 469 470 sc = device_get_softc(dev); 471 sc->lge_dev = dev; 472 473 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 474 MTX_DEF); 475 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0); 476 477 /* 478 * Map control/status registers. 479 */ 480 pci_enable_busmaster(dev); 481 482 rid = LGE_RID; 483 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 484 485 if (sc->lge_res == NULL) { 486 device_printf(dev, "couldn't map ports/memory\n"); 487 error = ENXIO; 488 goto fail; 489 } 490 491 sc->lge_btag = rman_get_bustag(sc->lge_res); 492 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 493 494 /* Allocate interrupt */ 495 rid = 0; 496 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 497 RF_SHAREABLE | RF_ACTIVE); 498 499 if (sc->lge_irq == NULL) { 500 device_printf(dev, "couldn't map interrupt\n"); 501 error = ENXIO; 502 goto fail; 503 } 504 505 /* Reset the adapter. */ 506 lge_reset(sc); 507 508 /* 509 * Get station address from the EEPROM. 510 */ 511 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 512 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 513 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 514 515 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 516 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 517 518 if (sc->lge_ldata == NULL) { 519 device_printf(dev, "no memory for list buffers!\n"); 520 error = ENXIO; 521 goto fail; 522 } 523 524 /* Try to allocate memory for jumbo buffers. */ 525 if (lge_alloc_jumbo_mem(sc)) { 526 device_printf(dev, "jumbo buffer allocation failed\n"); 527 error = ENXIO; 528 goto fail; 529 } 530 531 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 532 if (ifp == NULL) { 533 device_printf(dev, "can not if_alloc()\n"); 534 error = ENOSPC; 535 goto fail; 536 } 537 ifp->if_softc = sc; 538 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 539 ifp->if_mtu = ETHERMTU; 540 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 541 ifp->if_ioctl = lge_ioctl; 542 ifp->if_start = lge_start; 543 ifp->if_init = lge_init; 544 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 545 ifp->if_capabilities = IFCAP_RXCSUM; 546 ifp->if_capenable = ifp->if_capabilities; 547 548 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 549 sc->lge_pcs = 1; 550 else 551 sc->lge_pcs = 0; 552 553 /* 554 * Do MII setup. 555 */ 556 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd, 557 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 558 if (error != 0) { 559 device_printf(dev, "attaching PHYs failed\n"); 560 goto fail; 561 } 562 563 /* 564 * Call MI attach routine. 565 */ 566 ether_ifattach(ifp, eaddr); 567 568 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE, 569 NULL, lge_intr, sc, &sc->lge_intrhand); 570 571 if (error) { 572 ether_ifdetach(ifp); 573 device_printf(dev, "couldn't set up irq\n"); 574 goto fail; 575 } 576 return (0); 577 578fail: 579 lge_free_jumbo_mem(sc); 580 if (sc->lge_ldata) 581 contigfree(sc->lge_ldata, 582 sizeof(struct lge_list_data), M_DEVBUF); 583 if (ifp) 584 if_free(ifp); 585 if (sc->lge_irq) 586 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 587 if (sc->lge_res) 588 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 589 mtx_destroy(&sc->lge_mtx); 590 return(error); 591} 592 593static int 594lge_detach(dev) 595 device_t dev; 596{ 597 struct lge_softc *sc; 598 struct ifnet *ifp; 599 600 sc = device_get_softc(dev); 601 ifp = sc->lge_ifp; 602 603 LGE_LOCK(sc); 604 lge_reset(sc); 605 lge_stop(sc); 606 LGE_UNLOCK(sc); 607 callout_drain(&sc->lge_stat_callout); 608 ether_ifdetach(ifp); 609 610 bus_generic_detach(dev); 611 device_delete_child(dev, sc->lge_miibus); 612 613 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 614 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 615 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 616 617 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 618 if_free(ifp); 619 lge_free_jumbo_mem(sc); 620 mtx_destroy(&sc->lge_mtx); 621 622 return(0); 623} 624 625/* 626 * Initialize the transmit descriptors. 627 */ 628static int 629lge_list_tx_init(sc) 630 struct lge_softc *sc; 631{ 632 struct lge_list_data *ld; 633 struct lge_ring_data *cd; 634 int i; 635 636 cd = &sc->lge_cdata; 637 ld = sc->lge_ldata; 638 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 639 ld->lge_tx_list[i].lge_mbuf = NULL; 640 ld->lge_tx_list[i].lge_ctl = 0; 641 } 642 643 cd->lge_tx_prod = cd->lge_tx_cons = 0; 644 645 return(0); 646} 647 648 649/* 650 * Initialize the RX descriptors and allocate mbufs for them. Note that 651 * we arralge the descriptors in a closed ring, so that the last descriptor 652 * points back to the first. 653 */ 654static int 655lge_list_rx_init(sc) 656 struct lge_softc *sc; 657{ 658 struct lge_list_data *ld; 659 struct lge_ring_data *cd; 660 int i; 661 662 ld = sc->lge_ldata; 663 cd = &sc->lge_cdata; 664 665 cd->lge_rx_prod = cd->lge_rx_cons = 0; 666 667 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 668 669 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 670 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 671 break; 672 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 673 return(ENOBUFS); 674 } 675 676 /* Clear possible 'rx command queue empty' interrupt. */ 677 CSR_READ_4(sc, LGE_ISR); 678 679 return(0); 680} 681 682/* 683 * Initialize an RX descriptor and attach an MBUF cluster. 684 */ 685static int 686lge_newbuf(sc, c, m) 687 struct lge_softc *sc; 688 struct lge_rx_desc *c; 689 struct mbuf *m; 690{ 691 struct mbuf *m_new = NULL; 692 caddr_t *buf = NULL; 693 694 if (m == NULL) { 695 MGETHDR(m_new, M_NOWAIT, MT_DATA); 696 if (m_new == NULL) { 697 device_printf(sc->lge_dev, "no memory for rx list " 698 "-- packet dropped!\n"); 699 return(ENOBUFS); 700 } 701 702 /* Allocate the jumbo buffer */ 703 buf = lge_jalloc(sc); 704 if (buf == NULL) { 705#ifdef LGE_VERBOSE 706 device_printf(sc->lge_dev, "jumbo allocation failed " 707 "-- packet dropped!\n"); 708#endif 709 m_freem(m_new); 710 return(ENOBUFS); 711 } 712 /* Attach the buffer to the mbuf */ 713 m_new->m_data = (void *)buf; 714 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 715 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 716 buf, (struct lge_softc *)sc, 0, EXT_NET_DRV); 717 } else { 718 m_new = m; 719 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 720 m_new->m_data = m_new->m_ext.ext_buf; 721 } 722 723 /* 724 * Adjust alignment so packet payload begins on a 725 * longword boundary. Mandatory for Alpha, useful on 726 * x86 too. 727 */ 728 m_adj(m_new, ETHER_ALIGN); 729 730 c->lge_mbuf = m_new; 731 c->lge_fragptr_hi = 0; 732 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 733 c->lge_fraglen = m_new->m_len; 734 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 735 c->lge_sts = 0; 736 737 /* 738 * Put this buffer in the RX command FIFO. To do this, 739 * we just write the physical address of the descriptor 740 * into the RX descriptor address registers. Note that 741 * there are two registers, one high DWORD and one low 742 * DWORD, which lets us specify a 64-bit address if 743 * desired. We only use a 32-bit address for now. 744 * Writing to the low DWORD register is what actually 745 * causes the command to be issued, so we do that 746 * last. 747 */ 748 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 749 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 750 751 return(0); 752} 753 754static int 755lge_alloc_jumbo_mem(sc) 756 struct lge_softc *sc; 757{ 758 caddr_t ptr; 759 register int i; 760 struct lge_jpool_entry *entry; 761 762 /* Grab a big chunk o' storage. */ 763 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 764 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 765 766 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 767 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n"); 768 return(ENOBUFS); 769 } 770 771 SLIST_INIT(&sc->lge_jfree_listhead); 772 SLIST_INIT(&sc->lge_jinuse_listhead); 773 774 /* 775 * Now divide it up into 9K pieces and save the addresses 776 * in an array. 777 */ 778 ptr = sc->lge_cdata.lge_jumbo_buf; 779 for (i = 0; i < LGE_JSLOTS; i++) { 780 sc->lge_cdata.lge_jslots[i] = ptr; 781 ptr += LGE_JLEN; 782 entry = malloc(sizeof(struct lge_jpool_entry), 783 M_DEVBUF, M_NOWAIT); 784 if (entry == NULL) { 785 device_printf(sc->lge_dev, "no memory for jumbo " 786 "buffer queue!\n"); 787 return(ENOBUFS); 788 } 789 entry->slot = i; 790 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 791 entry, jpool_entries); 792 } 793 794 return(0); 795} 796 797static void 798lge_free_jumbo_mem(sc) 799 struct lge_softc *sc; 800{ 801 struct lge_jpool_entry *entry; 802 803 if (sc->lge_cdata.lge_jumbo_buf == NULL) 804 return; 805 806 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) { 807 device_printf(sc->lge_dev, 808 "asked to free buffer that is in use!\n"); 809 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 810 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, 811 jpool_entries); 812 } 813 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) { 814 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 815 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 816 free(entry, M_DEVBUF); 817 } 818 819 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 820 821 return; 822} 823 824/* 825 * Allocate a jumbo buffer. 826 */ 827static void * 828lge_jalloc(sc) 829 struct lge_softc *sc; 830{ 831 struct lge_jpool_entry *entry; 832 833 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 834 835 if (entry == NULL) { 836#ifdef LGE_VERBOSE 837 device_printf(sc->lge_dev, "no free jumbo buffers\n"); 838#endif 839 return(NULL); 840 } 841 842 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 843 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 844 return(sc->lge_cdata.lge_jslots[entry->slot]); 845} 846 847/* 848 * Release a jumbo buffer. 849 */ 850static void 851lge_jfree(buf, args) 852 void *buf; 853 void *args; 854{ 855 struct lge_softc *sc; 856 int i; 857 struct lge_jpool_entry *entry; 858 859 /* Extract the softc struct pointer. */ 860 sc = args; 861 862 if (sc == NULL) 863 panic("lge_jfree: can't find softc pointer!"); 864 865 /* calculate the slot this buffer belongs to */ 866 i = ((vm_offset_t)buf 867 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 868 869 if ((i < 0) || (i >= LGE_JSLOTS)) 870 panic("lge_jfree: asked to free buffer that we don't manage!"); 871 872 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 873 if (entry == NULL) 874 panic("lge_jfree: buffer not in use!"); 875 entry->slot = i; 876 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 877 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 878 879 return; 880} 881 882/* 883 * A frame has been uploaded: pass the resulting mbuf chain up to 884 * the higher level protocols. 885 */ 886static void 887lge_rxeof(sc, cnt) 888 struct lge_softc *sc; 889 int cnt; 890{ 891 struct mbuf *m; 892 struct ifnet *ifp; 893 struct lge_rx_desc *cur_rx; 894 int c, i, total_len = 0; 895 u_int32_t rxsts, rxctl; 896 897 ifp = sc->lge_ifp; 898 899 /* Find out how many frames were processed. */ 900 c = cnt; 901 i = sc->lge_cdata.lge_rx_cons; 902 903 /* Suck them in. */ 904 while(c) { 905 struct mbuf *m0 = NULL; 906 907 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 908 rxctl = cur_rx->lge_ctl; 909 rxsts = cur_rx->lge_sts; 910 m = cur_rx->lge_mbuf; 911 cur_rx->lge_mbuf = NULL; 912 total_len = LGE_RXBYTES(cur_rx); 913 LGE_INC(i, LGE_RX_LIST_CNT); 914 c--; 915 916 /* 917 * If an error occurs, update stats, clear the 918 * status word and leave the mbuf cluster in place: 919 * it should simply get re-used next time this descriptor 920 * comes up in the ring. 921 */ 922 if (rxctl & LGE_RXCTL_ERRMASK) { 923 ifp->if_ierrors++; 924 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 925 continue; 926 } 927 928 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 929 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 930 ifp, NULL); 931 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 932 if (m0 == NULL) { 933 device_printf(sc->lge_dev, "no receive buffers " 934 "available -- packet dropped!\n"); 935 ifp->if_ierrors++; 936 continue; 937 } 938 m = m0; 939 } else { 940 m->m_pkthdr.rcvif = ifp; 941 m->m_pkthdr.len = m->m_len = total_len; 942 } 943 944 ifp->if_ipackets++; 945 946 /* Do IP checksum checking. */ 947 if (rxsts & LGE_RXSTS_ISIP) 948 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 949 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 950 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 951 if ((rxsts & LGE_RXSTS_ISTCP && 952 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 953 (rxsts & LGE_RXSTS_ISUDP && 954 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 955 m->m_pkthdr.csum_flags |= 956 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 957 m->m_pkthdr.csum_data = 0xffff; 958 } 959 960 LGE_UNLOCK(sc); 961 (*ifp->if_input)(ifp, m); 962 LGE_LOCK(sc); 963 } 964 965 sc->lge_cdata.lge_rx_cons = i; 966 967 return; 968} 969 970static void 971lge_rxeoc(sc) 972 struct lge_softc *sc; 973{ 974 struct ifnet *ifp; 975 976 ifp = sc->lge_ifp; 977 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 978 lge_init_locked(sc); 979 return; 980} 981 982/* 983 * A frame was downloaded to the chip. It's safe for us to clean up 984 * the list buffers. 985 */ 986 987static void 988lge_txeof(sc) 989 struct lge_softc *sc; 990{ 991 struct lge_tx_desc *cur_tx = NULL; 992 struct ifnet *ifp; 993 u_int32_t idx, txdone; 994 995 ifp = sc->lge_ifp; 996 997 /* Clear the timeout timer. */ 998 sc->lge_timer = 0; 999 1000 /* 1001 * Go through our tx list and free mbufs for those 1002 * frames that have been transmitted. 1003 */ 1004 idx = sc->lge_cdata.lge_tx_cons; 1005 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1006 1007 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1008 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1009 1010 ifp->if_opackets++; 1011 if (cur_tx->lge_mbuf != NULL) { 1012 m_freem(cur_tx->lge_mbuf); 1013 cur_tx->lge_mbuf = NULL; 1014 } 1015 cur_tx->lge_ctl = 0; 1016 1017 txdone--; 1018 LGE_INC(idx, LGE_TX_LIST_CNT); 1019 sc->lge_timer = 0; 1020 } 1021 1022 sc->lge_cdata.lge_tx_cons = idx; 1023 1024 if (cur_tx != NULL) 1025 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1026 1027 return; 1028} 1029 1030static void 1031lge_tick(xsc) 1032 void *xsc; 1033{ 1034 struct lge_softc *sc; 1035 struct mii_data *mii; 1036 struct ifnet *ifp; 1037 1038 sc = xsc; 1039 ifp = sc->lge_ifp; 1040 LGE_LOCK_ASSERT(sc); 1041 1042 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1043 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1044 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1045 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1046 1047 if (!sc->lge_link) { 1048 mii = device_get_softc(sc->lge_miibus); 1049 mii_tick(mii); 1050 if (mii->mii_media_status & IFM_ACTIVE && 1051 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1052 sc->lge_link++; 1053 if (bootverbose && 1054 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1055 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1056 device_printf(sc->lge_dev, "gigabit link up\n"); 1057 if (ifp->if_snd.ifq_head != NULL) 1058 lge_start_locked(ifp); 1059 } 1060 } 1061 1062 if (sc->lge_timer != 0 && --sc->lge_timer == 0) 1063 lge_watchdog(sc); 1064 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1065 1066 return; 1067} 1068 1069static void 1070lge_intr(arg) 1071 void *arg; 1072{ 1073 struct lge_softc *sc; 1074 struct ifnet *ifp; 1075 u_int32_t status; 1076 1077 sc = arg; 1078 ifp = sc->lge_ifp; 1079 LGE_LOCK(sc); 1080 1081 /* Supress unwanted interrupts */ 1082 if (!(ifp->if_flags & IFF_UP)) { 1083 lge_stop(sc); 1084 LGE_UNLOCK(sc); 1085 return; 1086 } 1087 1088 for (;;) { 1089 /* 1090 * Reading the ISR register clears all interrupts, and 1091 * clears the 'interrupts enabled' bit in the IMR 1092 * register. 1093 */ 1094 status = CSR_READ_4(sc, LGE_ISR); 1095 1096 if ((status & LGE_INTRS) == 0) 1097 break; 1098 1099 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1100 lge_txeof(sc); 1101 1102 if (status & LGE_ISR_RXDMA_DONE) 1103 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1104 1105 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1106 lge_rxeoc(sc); 1107 1108 if (status & LGE_ISR_PHY_INTR) { 1109 sc->lge_link = 0; 1110 callout_stop(&sc->lge_stat_callout); 1111 lge_tick(sc); 1112 } 1113 } 1114 1115 /* Re-enable interrupts. */ 1116 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1117 1118 if (ifp->if_snd.ifq_head != NULL) 1119 lge_start_locked(ifp); 1120 1121 LGE_UNLOCK(sc); 1122 return; 1123} 1124 1125/* 1126 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1127 * pointers to the fragment pointers. 1128 */ 1129static int 1130lge_encap(sc, m_head, txidx) 1131 struct lge_softc *sc; 1132 struct mbuf *m_head; 1133 u_int32_t *txidx; 1134{ 1135 struct lge_frag *f = NULL; 1136 struct lge_tx_desc *cur_tx; 1137 struct mbuf *m; 1138 int frag = 0, tot_len = 0; 1139 1140 /* 1141 * Start packing the mbufs in this chain into 1142 * the fragment pointers. Stop when we run out 1143 * of fragments or hit the end of the mbuf chain. 1144 */ 1145 m = m_head; 1146 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1147 frag = 0; 1148 1149 for (m = m_head; m != NULL; m = m->m_next) { 1150 if (m->m_len != 0) { 1151 tot_len += m->m_len; 1152 f = &cur_tx->lge_frags[frag]; 1153 f->lge_fraglen = m->m_len; 1154 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1155 f->lge_fragptr_hi = 0; 1156 frag++; 1157 } 1158 } 1159 1160 if (m != NULL) 1161 return(ENOBUFS); 1162 1163 cur_tx->lge_mbuf = m_head; 1164 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1165 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1166 1167 /* Queue for transmit */ 1168 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1169 1170 return(0); 1171} 1172 1173/* 1174 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1175 * to the mbuf data regions directly in the transmit lists. We also save a 1176 * copy of the pointers since the transmit list fragment pointers are 1177 * physical addresses. 1178 */ 1179 1180static void 1181lge_start(ifp) 1182 struct ifnet *ifp; 1183{ 1184 struct lge_softc *sc; 1185 1186 sc = ifp->if_softc; 1187 LGE_LOCK(sc); 1188 lge_start_locked(ifp); 1189 LGE_UNLOCK(sc); 1190} 1191 1192static void 1193lge_start_locked(ifp) 1194 struct ifnet *ifp; 1195{ 1196 struct lge_softc *sc; 1197 struct mbuf *m_head = NULL; 1198 u_int32_t idx; 1199 1200 sc = ifp->if_softc; 1201 1202 if (!sc->lge_link) 1203 return; 1204 1205 idx = sc->lge_cdata.lge_tx_prod; 1206 1207 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1208 return; 1209 1210 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1211 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1212 break; 1213 1214 IF_DEQUEUE(&ifp->if_snd, m_head); 1215 if (m_head == NULL) 1216 break; 1217 1218 if (lge_encap(sc, m_head, &idx)) { 1219 IF_PREPEND(&ifp->if_snd, m_head); 1220 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1221 break; 1222 } 1223 1224 /* 1225 * If there's a BPF listener, bounce a copy of this frame 1226 * to him. 1227 */ 1228 BPF_MTAP(ifp, m_head); 1229 } 1230 1231 sc->lge_cdata.lge_tx_prod = idx; 1232 1233 /* 1234 * Set a timeout in case the chip goes out to lunch. 1235 */ 1236 sc->lge_timer = 5; 1237 1238 return; 1239} 1240 1241static void 1242lge_init(xsc) 1243 void *xsc; 1244{ 1245 struct lge_softc *sc = xsc; 1246 1247 LGE_LOCK(sc); 1248 lge_init_locked(sc); 1249 LGE_UNLOCK(sc); 1250} 1251 1252static void 1253lge_init_locked(sc) 1254 struct lge_softc *sc; 1255{ 1256 struct ifnet *ifp = sc->lge_ifp; 1257 1258 LGE_LOCK_ASSERT(sc); 1259 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1260 return; 1261 1262 /* 1263 * Cancel pending I/O and free all RX/TX buffers. 1264 */ 1265 lge_stop(sc); 1266 lge_reset(sc); 1267 1268 /* Set MAC address */ 1269 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0])); 1270 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4])); 1271 1272 /* Init circular RX list. */ 1273 if (lge_list_rx_init(sc) == ENOBUFS) { 1274 device_printf(sc->lge_dev, "initialization failed: no " 1275 "memory for rx buffers\n"); 1276 lge_stop(sc); 1277 return; 1278 } 1279 1280 /* 1281 * Init tx descriptors. 1282 */ 1283 lge_list_tx_init(sc); 1284 1285 /* Set initial value for MODE1 register. */ 1286 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1287 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1288 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1289 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1290 1291 /* If we want promiscuous mode, set the allframes bit. */ 1292 if (ifp->if_flags & IFF_PROMISC) { 1293 CSR_WRITE_4(sc, LGE_MODE1, 1294 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1295 } else { 1296 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1297 } 1298 1299 /* 1300 * Set the capture broadcast bit to capture broadcast frames. 1301 */ 1302 if (ifp->if_flags & IFF_BROADCAST) { 1303 CSR_WRITE_4(sc, LGE_MODE1, 1304 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1305 } else { 1306 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1307 } 1308 1309 /* Packet padding workaround? */ 1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1311 1312 /* No error frames */ 1313 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1314 1315 /* Receive large frames */ 1316 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1317 1318 /* Workaround: disable RX/TX flow control */ 1319 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1320 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1321 1322 /* Make sure to strip CRC from received frames */ 1323 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1324 1325 /* Turn off magic packet mode */ 1326 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1327 1328 /* Turn off all VLAN stuff */ 1329 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1330 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1331 1332 /* Workarond: FIFO overflow */ 1333 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1334 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1335 1336 /* 1337 * Load the multicast filter. 1338 */ 1339 lge_setmulti(sc); 1340 1341 /* 1342 * Enable hardware checksum validation for all received IPv4 1343 * packets, do not reject packets with bad checksums. 1344 */ 1345 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1346 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1347 LGE_MODE2_RX_ERRCSUM); 1348 1349 /* 1350 * Enable the delivery of PHY interrupts based on 1351 * link/speed/duplex status chalges. 1352 */ 1353 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1354 1355 /* Enable receiver and transmitter. */ 1356 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1358 1359 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1360 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1361 1362 /* 1363 * Enable interrupts. 1364 */ 1365 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1366 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1367 1368 lge_ifmedia_upd_locked(ifp); 1369 1370 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1371 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1372 1373 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1374 1375 return; 1376} 1377 1378/* 1379 * Set media options. 1380 */ 1381static int 1382lge_ifmedia_upd(ifp) 1383 struct ifnet *ifp; 1384{ 1385 struct lge_softc *sc; 1386 1387 sc = ifp->if_softc; 1388 LGE_LOCK(sc); 1389 lge_ifmedia_upd_locked(ifp); 1390 LGE_UNLOCK(sc); 1391 1392 return(0); 1393} 1394 1395static void 1396lge_ifmedia_upd_locked(ifp) 1397 struct ifnet *ifp; 1398{ 1399 struct lge_softc *sc; 1400 struct mii_data *mii; 1401 struct mii_softc *miisc; 1402 1403 sc = ifp->if_softc; 1404 1405 LGE_LOCK_ASSERT(sc); 1406 mii = device_get_softc(sc->lge_miibus); 1407 sc->lge_link = 0; 1408 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1409 PHY_RESET(miisc); 1410 mii_mediachg(mii); 1411} 1412 1413/* 1414 * Report current media status. 1415 */ 1416static void 1417lge_ifmedia_sts(ifp, ifmr) 1418 struct ifnet *ifp; 1419 struct ifmediareq *ifmr; 1420{ 1421 struct lge_softc *sc; 1422 struct mii_data *mii; 1423 1424 sc = ifp->if_softc; 1425 1426 LGE_LOCK(sc); 1427 mii = device_get_softc(sc->lge_miibus); 1428 mii_pollstat(mii); 1429 ifmr->ifm_active = mii->mii_media_active; 1430 ifmr->ifm_status = mii->mii_media_status; 1431 LGE_UNLOCK(sc); 1432 1433 return; 1434} 1435 1436static int 1437lge_ioctl(ifp, command, data) 1438 struct ifnet *ifp; 1439 u_long command; 1440 caddr_t data; 1441{ 1442 struct lge_softc *sc = ifp->if_softc; 1443 struct ifreq *ifr = (struct ifreq *) data; 1444 struct mii_data *mii; 1445 int error = 0; 1446 1447 switch(command) { 1448 case SIOCSIFMTU: 1449 LGE_LOCK(sc); 1450 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1451 error = EINVAL; 1452 else 1453 ifp->if_mtu = ifr->ifr_mtu; 1454 LGE_UNLOCK(sc); 1455 break; 1456 case SIOCSIFFLAGS: 1457 LGE_LOCK(sc); 1458 if (ifp->if_flags & IFF_UP) { 1459 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1460 ifp->if_flags & IFF_PROMISC && 1461 !(sc->lge_if_flags & IFF_PROMISC)) { 1462 CSR_WRITE_4(sc, LGE_MODE1, 1463 LGE_MODE1_SETRST_CTL1| 1464 LGE_MODE1_RX_PROMISC); 1465 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1466 !(ifp->if_flags & IFF_PROMISC) && 1467 sc->lge_if_flags & IFF_PROMISC) { 1468 CSR_WRITE_4(sc, LGE_MODE1, 1469 LGE_MODE1_RX_PROMISC); 1470 } else { 1471 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1472 lge_init_locked(sc); 1473 } 1474 } else { 1475 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1476 lge_stop(sc); 1477 } 1478 sc->lge_if_flags = ifp->if_flags; 1479 LGE_UNLOCK(sc); 1480 error = 0; 1481 break; 1482 case SIOCADDMULTI: 1483 case SIOCDELMULTI: 1484 LGE_LOCK(sc); 1485 lge_setmulti(sc); 1486 LGE_UNLOCK(sc); 1487 error = 0; 1488 break; 1489 case SIOCGIFMEDIA: 1490 case SIOCSIFMEDIA: 1491 mii = device_get_softc(sc->lge_miibus); 1492 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1493 break; 1494 default: 1495 error = ether_ioctl(ifp, command, data); 1496 break; 1497 } 1498 1499 return(error); 1500} 1501 1502static void 1503lge_watchdog(sc) 1504 struct lge_softc *sc; 1505{ 1506 struct ifnet *ifp; 1507 1508 LGE_LOCK_ASSERT(sc); 1509 ifp = sc->lge_ifp; 1510 1511 ifp->if_oerrors++; 1512 if_printf(ifp, "watchdog timeout\n"); 1513 1514 lge_stop(sc); 1515 lge_reset(sc); 1516 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1517 lge_init_locked(sc); 1518 1519 if (ifp->if_snd.ifq_head != NULL) 1520 lge_start_locked(ifp); 1521} 1522 1523/* 1524 * Stop the adapter and free any mbufs allocated to the 1525 * RX and TX lists. 1526 */ 1527static void 1528lge_stop(sc) 1529 struct lge_softc *sc; 1530{ 1531 register int i; 1532 struct ifnet *ifp; 1533 1534 LGE_LOCK_ASSERT(sc); 1535 ifp = sc->lge_ifp; 1536 sc->lge_timer = 0; 1537 callout_stop(&sc->lge_stat_callout); 1538 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1539 1540 /* Disable receiver and transmitter. */ 1541 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1542 sc->lge_link = 0; 1543 1544 /* 1545 * Free data in the RX lists. 1546 */ 1547 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1548 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1549 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1550 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1551 } 1552 } 1553 bzero((char *)&sc->lge_ldata->lge_rx_list, 1554 sizeof(sc->lge_ldata->lge_rx_list)); 1555 1556 /* 1557 * Free the TX list buffers. 1558 */ 1559 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1560 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1561 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1562 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1563 } 1564 } 1565 1566 bzero((char *)&sc->lge_ldata->lge_tx_list, 1567 sizeof(sc->lge_ldata->lge_tx_list)); 1568 1569 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1570 1571 return; 1572} 1573 1574/* 1575 * Stop all chip I/O so that the kernel's probe routines don't 1576 * get confused by errant DMAs when rebooting. 1577 */ 1578static int 1579lge_shutdown(dev) 1580 device_t dev; 1581{ 1582 struct lge_softc *sc; 1583 1584 sc = device_get_softc(dev); 1585 1586 LGE_LOCK(sc); 1587 lge_reset(sc); 1588 lge_stop(sc); 1589 LGE_UNLOCK(sc); 1590 1591 return (0); 1592} 1593