1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD$"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/module.h> 92#include <sys/kernel.h> 93#include <sys/socket.h> 94#include <sys/queue.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <dev/pci/pcireg.h> 113#include <dev/pci/pcivar.h> 114 115#include <dev/mii/mii.h> 116#include <dev/mii/mii_bitbang.h> 117#include <dev/mii/miivar.h> 118 119/* "device miibus" required. See GENERIC if you get errors here. */ 120#include "miibus_if.h" 121 122#define WB_USEIOSPACE 123 124#include <dev/wb/if_wbreg.h> 125 126MODULE_DEPEND(wb, pci, 1, 1, 1); 127MODULE_DEPEND(wb, ether, 1, 1, 1); 128MODULE_DEPEND(wb, miibus, 1, 1, 1); 129 130/* 131 * Various supported device vendors/types and their names. 132 */ 133static const struct wb_type wb_devs[] = { 134 { WB_VENDORID, WB_DEVICEID_840F, 135 "Winbond W89C840F 10/100BaseTX" }, 136 { CP_VENDORID, CP_DEVICEID_RL100, 137 "Compex RL100-ATX 10/100baseTX" }, 138 { 0, 0, NULL } 139}; 140 141static int wb_probe(device_t); 142static int wb_attach(device_t); 143static int wb_detach(device_t); 144 145static void wb_bfree(void *addr, void *args); 146static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 147 struct mbuf *); 148static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 149 150static void wb_rxeof(struct wb_softc *); 151static void wb_rxeoc(struct wb_softc *); 152static void wb_txeof(struct wb_softc *); 153static void wb_txeoc(struct wb_softc *); 154static void wb_intr(void *); 155static void wb_tick(void *); 156static void wb_start(struct ifnet *); 157static void wb_start_locked(struct ifnet *); 158static int wb_ioctl(struct ifnet *, u_long, caddr_t); 159static void wb_init(void *); 160static void wb_init_locked(struct wb_softc *); 161static void wb_stop(struct wb_softc *); 162static void wb_watchdog(struct wb_softc *); 163static int wb_shutdown(device_t); 164static int wb_ifmedia_upd(struct ifnet *); 165static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 166 167static void wb_eeprom_putbyte(struct wb_softc *, int); 168static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 169static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 170 171static void wb_setcfg(struct wb_softc *, u_int32_t); 172static void wb_setmulti(struct wb_softc *); 173static void wb_reset(struct wb_softc *); 174static void wb_fixmedia(struct wb_softc *); 175static int wb_list_rx_init(struct wb_softc *); 176static int wb_list_tx_init(struct wb_softc *); 177 178static int wb_miibus_readreg(device_t, int, int); 179static int wb_miibus_writereg(device_t, int, int, int); 180static void wb_miibus_statchg(device_t); 181 182/* 183 * MII bit-bang glue 184 */ 185static uint32_t wb_mii_bitbang_read(device_t); 186static void wb_mii_bitbang_write(device_t, uint32_t); 187 188static const struct mii_bitbang_ops wb_mii_bitbang_ops = { 189 wb_mii_bitbang_read, 190 wb_mii_bitbang_write, 191 { 192 WB_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 193 WB_SIO_MII_DATAIN, /* MII_BIT_MDI */ 194 WB_SIO_MII_CLK, /* MII_BIT_MDC */ 195 WB_SIO_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 196 0, /* MII_BIT_DIR_PHY_HOST */ 197 } 198}; 199 200#ifdef WB_USEIOSPACE 201#define WB_RES SYS_RES_IOPORT 202#define WB_RID WB_PCI_LOIO 203#else 204#define WB_RES SYS_RES_MEMORY 205#define WB_RID WB_PCI_LOMEM 206#endif 207 208static device_method_t wb_methods[] = { 209 /* Device interface */ 210 DEVMETHOD(device_probe, wb_probe), 211 DEVMETHOD(device_attach, wb_attach), 212 DEVMETHOD(device_detach, wb_detach), 213 DEVMETHOD(device_shutdown, wb_shutdown), 214 215 /* MII interface */ 216 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 217 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 218 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 219 220 DEVMETHOD_END 221}; 222 223static driver_t wb_driver = { 224 "wb", 225 wb_methods, 226 sizeof(struct wb_softc) 227}; 228 229static devclass_t wb_devclass; 230 231DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 232DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 233 234#define WB_SETBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) | (x)) 237 238#define WB_CLRBIT(sc, reg, x) \ 239 CSR_WRITE_4(sc, reg, \ 240 CSR_READ_4(sc, reg) & ~(x)) 241 242#define SIO_SET(x) \ 243 CSR_WRITE_4(sc, WB_SIO, \ 244 CSR_READ_4(sc, WB_SIO) | (x)) 245 246#define SIO_CLR(x) \ 247 CSR_WRITE_4(sc, WB_SIO, \ 248 CSR_READ_4(sc, WB_SIO) & ~(x)) 249 250/* 251 * Send a read command and address to the EEPROM, check for ACK. 252 */ 253static void 254wb_eeprom_putbyte(sc, addr) 255 struct wb_softc *sc; 256 int addr; 257{ 258 register int d, i; 259 260 d = addr | WB_EECMD_READ; 261 262 /* 263 * Feed in each bit and stobe the clock. 264 */ 265 for (i = 0x400; i; i >>= 1) { 266 if (d & i) { 267 SIO_SET(WB_SIO_EE_DATAIN); 268 } else { 269 SIO_CLR(WB_SIO_EE_DATAIN); 270 } 271 DELAY(100); 272 SIO_SET(WB_SIO_EE_CLK); 273 DELAY(150); 274 SIO_CLR(WB_SIO_EE_CLK); 275 DELAY(100); 276 } 277} 278 279/* 280 * Read a word of data stored in the EEPROM at address 'addr.' 281 */ 282static void 283wb_eeprom_getword(sc, addr, dest) 284 struct wb_softc *sc; 285 int addr; 286 u_int16_t *dest; 287{ 288 register int i; 289 u_int16_t word = 0; 290 291 /* Enter EEPROM access mode. */ 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Send address of word we want to read. 296 */ 297 wb_eeprom_putbyte(sc, addr); 298 299 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 300 301 /* 302 * Start reading bits from EEPROM. 303 */ 304 for (i = 0x8000; i; i >>= 1) { 305 SIO_SET(WB_SIO_EE_CLK); 306 DELAY(100); 307 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 308 word |= i; 309 SIO_CLR(WB_SIO_EE_CLK); 310 DELAY(100); 311 } 312 313 /* Turn off EEPROM access mode. */ 314 CSR_WRITE_4(sc, WB_SIO, 0); 315 316 *dest = word; 317} 318 319/* 320 * Read a sequence of words from the EEPROM. 321 */ 322static void 323wb_read_eeprom(sc, dest, off, cnt, swap) 324 struct wb_softc *sc; 325 caddr_t dest; 326 int off; 327 int cnt; 328 int swap; 329{ 330 int i; 331 u_int16_t word = 0, *ptr; 332 333 for (i = 0; i < cnt; i++) { 334 wb_eeprom_getword(sc, off + i, &word); 335 ptr = (u_int16_t *)(dest + (i * 2)); 336 if (swap) 337 *ptr = ntohs(word); 338 else 339 *ptr = word; 340 } 341} 342 343/* 344 * Read the MII serial port for the MII bit-bang module. 345 */ 346static uint32_t 347wb_mii_bitbang_read(device_t dev) 348{ 349 struct wb_softc *sc; 350 uint32_t val; 351 352 sc = device_get_softc(dev); 353 354 val = CSR_READ_4(sc, WB_SIO); 355 CSR_BARRIER(sc, WB_SIO, 4, 356 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 357 358 return (val); 359} 360 361/* 362 * Write the MII serial port for the MII bit-bang module. 363 */ 364static void 365wb_mii_bitbang_write(device_t dev, uint32_t val) 366{ 367 struct wb_softc *sc; 368 369 sc = device_get_softc(dev); 370 371 CSR_WRITE_4(sc, WB_SIO, val); 372 CSR_BARRIER(sc, WB_SIO, 4, 373 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 374} 375 376static int 377wb_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380{ 381 382 return (mii_bitbang_readreg(dev, &wb_mii_bitbang_ops, phy, reg)); 383} 384 385static int 386wb_miibus_writereg(dev, phy, reg, data) 387 device_t dev; 388 int phy, reg, data; 389{ 390 391 mii_bitbang_writereg(dev, &wb_mii_bitbang_ops, phy, reg, data); 392 393 return(0); 394} 395 396static void 397wb_miibus_statchg(dev) 398 device_t dev; 399{ 400 struct wb_softc *sc; 401 struct mii_data *mii; 402 403 sc = device_get_softc(dev); 404 mii = device_get_softc(sc->wb_miibus); 405 wb_setcfg(sc, mii->mii_media_active); 406} 407 408/* 409 * Program the 64-bit multicast hash filter. 410 */ 411static void 412wb_setmulti(sc) 413 struct wb_softc *sc; 414{ 415 struct ifnet *ifp; 416 int h = 0; 417 u_int32_t hashes[2] = { 0, 0 }; 418 struct ifmultiaddr *ifma; 419 u_int32_t rxfilt; 420 int mcnt = 0; 421 422 ifp = sc->wb_ifp; 423 424 rxfilt = CSR_READ_4(sc, WB_NETCFG); 425 426 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 427 rxfilt |= WB_NETCFG_RX_MULTI; 428 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 429 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 430 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 431 return; 432 } 433 434 /* first, zot all the existing hash bits */ 435 CSR_WRITE_4(sc, WB_MAR0, 0); 436 CSR_WRITE_4(sc, WB_MAR1, 0); 437 438 /* now program new ones */ 439 if_maddr_rlock(ifp); 440 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 441 if (ifma->ifma_addr->sa_family != AF_LINK) 442 continue; 443 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 444 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 445 if (h < 32) 446 hashes[0] |= (1 << h); 447 else 448 hashes[1] |= (1 << (h - 32)); 449 mcnt++; 450 } 451 if_maddr_runlock(ifp); 452 453 if (mcnt) 454 rxfilt |= WB_NETCFG_RX_MULTI; 455 else 456 rxfilt &= ~WB_NETCFG_RX_MULTI; 457 458 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 459 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 460 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 461} 462 463/* 464 * The Winbond manual states that in order to fiddle with the 465 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 466 * first have to put the transmit and/or receive logic in the idle state. 467 */ 468static void 469wb_setcfg(sc, media) 470 struct wb_softc *sc; 471 u_int32_t media; 472{ 473 int i, restart = 0; 474 475 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 476 restart = 1; 477 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 478 479 for (i = 0; i < WB_TIMEOUT; i++) { 480 DELAY(10); 481 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 482 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 483 break; 484 } 485 486 if (i == WB_TIMEOUT) 487 device_printf(sc->wb_dev, 488 "failed to force tx and rx to idle state\n"); 489 } 490 491 if (IFM_SUBTYPE(media) == IFM_10_T) 492 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 493 else 494 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 495 496 if ((media & IFM_GMASK) == IFM_FDX) 497 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 498 else 499 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 500 501 if (restart) 502 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 503} 504 505static void 506wb_reset(sc) 507 struct wb_softc *sc; 508{ 509 register int i; 510 struct mii_data *mii; 511 struct mii_softc *miisc; 512 513 CSR_WRITE_4(sc, WB_NETCFG, 0); 514 CSR_WRITE_4(sc, WB_BUSCTL, 0); 515 CSR_WRITE_4(sc, WB_TXADDR, 0); 516 CSR_WRITE_4(sc, WB_RXADDR, 0); 517 518 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 519 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 520 521 for (i = 0; i < WB_TIMEOUT; i++) { 522 DELAY(10); 523 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 524 break; 525 } 526 if (i == WB_TIMEOUT) 527 device_printf(sc->wb_dev, "reset never completed!\n"); 528 529 /* Wait a little while for the chip to get its brains in order. */ 530 DELAY(1000); 531 532 if (sc->wb_miibus == NULL) 533 return; 534 535 mii = device_get_softc(sc->wb_miibus); 536 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 537 PHY_RESET(miisc); 538} 539 540static void 541wb_fixmedia(sc) 542 struct wb_softc *sc; 543{ 544 struct mii_data *mii = NULL; 545 struct ifnet *ifp; 546 u_int32_t media; 547 548 mii = device_get_softc(sc->wb_miibus); 549 ifp = sc->wb_ifp; 550 551 mii_pollstat(mii); 552 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 553 media = mii->mii_media_active & ~IFM_10_T; 554 media |= IFM_100_TX; 555 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 556 media = mii->mii_media_active & ~IFM_100_TX; 557 media |= IFM_10_T; 558 } else 559 return; 560 561 ifmedia_set(&mii->mii_media, media); 562} 563 564/* 565 * Probe for a Winbond chip. Check the PCI vendor and device 566 * IDs against our list and return a device name if we find a match. 567 */ 568static int 569wb_probe(dev) 570 device_t dev; 571{ 572 const struct wb_type *t; 573 574 t = wb_devs; 575 576 while(t->wb_name != NULL) { 577 if ((pci_get_vendor(dev) == t->wb_vid) && 578 (pci_get_device(dev) == t->wb_did)) { 579 device_set_desc(dev, t->wb_name); 580 return (BUS_PROBE_DEFAULT); 581 } 582 t++; 583 } 584 585 return(ENXIO); 586} 587 588/* 589 * Attach the interface. Allocate softc structures, do ifmedia 590 * setup and ethernet/BPF attach. 591 */ 592static int 593wb_attach(dev) 594 device_t dev; 595{ 596 u_char eaddr[ETHER_ADDR_LEN]; 597 struct wb_softc *sc; 598 struct ifnet *ifp; 599 int error = 0, rid; 600 601 sc = device_get_softc(dev); 602 sc->wb_dev = dev; 603 604 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 605 MTX_DEF); 606 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0); 607 608 /* 609 * Map control/status registers. 610 */ 611 pci_enable_busmaster(dev); 612 613 rid = WB_RID; 614 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 615 616 if (sc->wb_res == NULL) { 617 device_printf(dev, "couldn't map ports/memory\n"); 618 error = ENXIO; 619 goto fail; 620 } 621 622 /* Allocate interrupt */ 623 rid = 0; 624 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 625 RF_SHAREABLE | RF_ACTIVE); 626 627 if (sc->wb_irq == NULL) { 628 device_printf(dev, "couldn't map interrupt\n"); 629 error = ENXIO; 630 goto fail; 631 } 632 633 /* Save the cache line size. */ 634 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 635 636 /* Reset the adapter. */ 637 wb_reset(sc); 638 639 /* 640 * Get station address from the EEPROM. 641 */ 642 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 643 644 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 645 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 646 647 if (sc->wb_ldata == NULL) { 648 device_printf(dev, "no memory for list buffers!\n"); 649 error = ENXIO; 650 goto fail; 651 } 652 653 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 654 655 ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 656 if (ifp == NULL) { 657 device_printf(dev, "can not if_alloc()\n"); 658 error = ENOSPC; 659 goto fail; 660 } 661 ifp->if_softc = sc; 662 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 663 ifp->if_mtu = ETHERMTU; 664 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 665 ifp->if_ioctl = wb_ioctl; 666 ifp->if_start = wb_start; 667 ifp->if_init = wb_init; 668 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 669 670 /* 671 * Do MII setup. 672 */ 673 error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd, 674 wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 675 if (error != 0) { 676 device_printf(dev, "attaching PHYs failed\n"); 677 goto fail; 678 } 679 680 /* 681 * Call MI attach routine. 682 */ 683 ether_ifattach(ifp, eaddr); 684 685 /* Hook interrupt last to avoid having to lock softc */ 686 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE, 687 NULL, wb_intr, sc, &sc->wb_intrhand); 688 689 if (error) { 690 device_printf(dev, "couldn't set up irq\n"); 691 ether_ifdetach(ifp); 692 goto fail; 693 } 694 695fail: 696 if (error) 697 wb_detach(dev); 698 699 return(error); 700} 701 702/* 703 * Shutdown hardware and free up resources. This can be called any 704 * time after the mutex has been initialized. It is called in both 705 * the error case in attach and the normal detach case so it needs 706 * to be careful about only freeing resources that have actually been 707 * allocated. 708 */ 709static int 710wb_detach(dev) 711 device_t dev; 712{ 713 struct wb_softc *sc; 714 struct ifnet *ifp; 715 716 sc = device_get_softc(dev); 717 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 718 ifp = sc->wb_ifp; 719 720 /* 721 * Delete any miibus and phy devices attached to this interface. 722 * This should only be done if attach succeeded. 723 */ 724 if (device_is_attached(dev)) { 725 ether_ifdetach(ifp); 726 WB_LOCK(sc); 727 wb_stop(sc); 728 WB_UNLOCK(sc); 729 callout_drain(&sc->wb_stat_callout); 730 } 731 if (sc->wb_miibus) 732 device_delete_child(dev, sc->wb_miibus); 733 bus_generic_detach(dev); 734 735 if (sc->wb_intrhand) 736 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 737 if (sc->wb_irq) 738 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 739 if (sc->wb_res) 740 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 741 742 if (ifp) 743 if_free(ifp); 744 745 if (sc->wb_ldata) { 746 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 747 M_DEVBUF); 748 } 749 750 mtx_destroy(&sc->wb_mtx); 751 752 return(0); 753} 754 755/* 756 * Initialize the transmit descriptors. 757 */ 758static int 759wb_list_tx_init(sc) 760 struct wb_softc *sc; 761{ 762 struct wb_chain_data *cd; 763 struct wb_list_data *ld; 764 int i; 765 766 cd = &sc->wb_cdata; 767 ld = sc->wb_ldata; 768 769 for (i = 0; i < WB_TX_LIST_CNT; i++) { 770 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 771 if (i == (WB_TX_LIST_CNT - 1)) { 772 cd->wb_tx_chain[i].wb_nextdesc = 773 &cd->wb_tx_chain[0]; 774 } else { 775 cd->wb_tx_chain[i].wb_nextdesc = 776 &cd->wb_tx_chain[i + 1]; 777 } 778 } 779 780 cd->wb_tx_free = &cd->wb_tx_chain[0]; 781 cd->wb_tx_tail = cd->wb_tx_head = NULL; 782 783 return(0); 784} 785 786 787/* 788 * Initialize the RX descriptors and allocate mbufs for them. Note that 789 * we arrange the descriptors in a closed ring, so that the last descriptor 790 * points back to the first. 791 */ 792static int 793wb_list_rx_init(sc) 794 struct wb_softc *sc; 795{ 796 struct wb_chain_data *cd; 797 struct wb_list_data *ld; 798 int i; 799 800 cd = &sc->wb_cdata; 801 ld = sc->wb_ldata; 802 803 for (i = 0; i < WB_RX_LIST_CNT; i++) { 804 cd->wb_rx_chain[i].wb_ptr = 805 (struct wb_desc *)&ld->wb_rx_list[i]; 806 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 807 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 808 return(ENOBUFS); 809 if (i == (WB_RX_LIST_CNT - 1)) { 810 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 811 ld->wb_rx_list[i].wb_next = 812 vtophys(&ld->wb_rx_list[0]); 813 } else { 814 cd->wb_rx_chain[i].wb_nextdesc = 815 &cd->wb_rx_chain[i + 1]; 816 ld->wb_rx_list[i].wb_next = 817 vtophys(&ld->wb_rx_list[i + 1]); 818 } 819 } 820 821 cd->wb_rx_head = &cd->wb_rx_chain[0]; 822 823 return(0); 824} 825 826static void 827wb_bfree(buf, args) 828 void *buf; 829 void *args; 830{ 831 832} 833 834/* 835 * Initialize an RX descriptor and attach an MBUF cluster. 836 */ 837static int 838wb_newbuf(sc, c, m) 839 struct wb_softc *sc; 840 struct wb_chain_onefrag *c; 841 struct mbuf *m; 842{ 843 struct mbuf *m_new = NULL; 844 845 if (m == NULL) { 846 MGETHDR(m_new, M_NOWAIT, MT_DATA); 847 if (m_new == NULL) 848 return(ENOBUFS); 849 m_new->m_data = c->wb_buf; 850 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 851 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf, 852 NULL, 0, EXT_NET_DRV); 853 } else { 854 m_new = m; 855 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 856 m_new->m_data = m_new->m_ext.ext_buf; 857 } 858 859 m_adj(m_new, sizeof(u_int64_t)); 860 861 c->wb_mbuf = m_new; 862 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 863 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 864 c->wb_ptr->wb_status = WB_RXSTAT; 865 866 return(0); 867} 868 869/* 870 * A frame has been uploaded: pass the resulting mbuf chain up to 871 * the higher level protocols. 872 */ 873static void 874wb_rxeof(sc) 875 struct wb_softc *sc; 876{ 877 struct mbuf *m = NULL; 878 struct ifnet *ifp; 879 struct wb_chain_onefrag *cur_rx; 880 int total_len = 0; 881 u_int32_t rxstat; 882 883 WB_LOCK_ASSERT(sc); 884 885 ifp = sc->wb_ifp; 886 887 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 888 WB_RXSTAT_OWN)) { 889 struct mbuf *m0 = NULL; 890 891 cur_rx = sc->wb_cdata.wb_rx_head; 892 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 893 894 m = cur_rx->wb_mbuf; 895 896 if ((rxstat & WB_RXSTAT_MIIERR) || 897 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 898 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 899 !(rxstat & WB_RXSTAT_LASTFRAG) || 900 !(rxstat & WB_RXSTAT_RXCMP)) { 901 ifp->if_ierrors++; 902 wb_newbuf(sc, cur_rx, m); 903 device_printf(sc->wb_dev, 904 "receiver babbling: possible chip bug," 905 " forcing reset\n"); 906 wb_fixmedia(sc); 907 wb_reset(sc); 908 wb_init_locked(sc); 909 return; 910 } 911 912 if (rxstat & WB_RXSTAT_RXERR) { 913 ifp->if_ierrors++; 914 wb_newbuf(sc, cur_rx, m); 915 break; 916 } 917 918 /* No errors; receive the packet. */ 919 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 920 921 /* 922 * XXX The Winbond chip includes the CRC with every 923 * received frame, and there's no way to turn this 924 * behavior off (at least, I can't find anything in 925 * the manual that explains how to do it) so we have 926 * to trim off the CRC manually. 927 */ 928 total_len -= ETHER_CRC_LEN; 929 930 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 931 NULL); 932 wb_newbuf(sc, cur_rx, m); 933 if (m0 == NULL) { 934 ifp->if_ierrors++; 935 break; 936 } 937 m = m0; 938 939 ifp->if_ipackets++; 940 WB_UNLOCK(sc); 941 (*ifp->if_input)(ifp, m); 942 WB_LOCK(sc); 943 } 944} 945 946static void 947wb_rxeoc(sc) 948 struct wb_softc *sc; 949{ 950 wb_rxeof(sc); 951 952 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 953 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 954 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 955 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 956 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 957} 958 959/* 960 * A frame was downloaded to the chip. It's safe for us to clean up 961 * the list buffers. 962 */ 963static void 964wb_txeof(sc) 965 struct wb_softc *sc; 966{ 967 struct wb_chain *cur_tx; 968 struct ifnet *ifp; 969 970 ifp = sc->wb_ifp; 971 972 /* Clear the timeout timer. */ 973 sc->wb_timer = 0; 974 975 if (sc->wb_cdata.wb_tx_head == NULL) 976 return; 977 978 /* 979 * Go through our tx list and free mbufs for those 980 * frames that have been transmitted. 981 */ 982 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 983 u_int32_t txstat; 984 985 cur_tx = sc->wb_cdata.wb_tx_head; 986 txstat = WB_TXSTATUS(cur_tx); 987 988 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 989 break; 990 991 if (txstat & WB_TXSTAT_TXERR) { 992 ifp->if_oerrors++; 993 if (txstat & WB_TXSTAT_ABORT) 994 ifp->if_collisions++; 995 if (txstat & WB_TXSTAT_LATECOLL) 996 ifp->if_collisions++; 997 } 998 999 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1000 1001 ifp->if_opackets++; 1002 m_freem(cur_tx->wb_mbuf); 1003 cur_tx->wb_mbuf = NULL; 1004 1005 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1006 sc->wb_cdata.wb_tx_head = NULL; 1007 sc->wb_cdata.wb_tx_tail = NULL; 1008 break; 1009 } 1010 1011 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1012 } 1013} 1014 1015/* 1016 * TX 'end of channel' interrupt handler. 1017 */ 1018static void 1019wb_txeoc(sc) 1020 struct wb_softc *sc; 1021{ 1022 struct ifnet *ifp; 1023 1024 ifp = sc->wb_ifp; 1025 1026 sc->wb_timer = 0; 1027 1028 if (sc->wb_cdata.wb_tx_head == NULL) { 1029 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1030 sc->wb_cdata.wb_tx_tail = NULL; 1031 } else { 1032 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1033 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1034 sc->wb_timer = 5; 1035 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1036 } 1037 } 1038} 1039 1040static void 1041wb_intr(arg) 1042 void *arg; 1043{ 1044 struct wb_softc *sc; 1045 struct ifnet *ifp; 1046 u_int32_t status; 1047 1048 sc = arg; 1049 WB_LOCK(sc); 1050 ifp = sc->wb_ifp; 1051 1052 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1053 WB_UNLOCK(sc); 1054 return; 1055 } 1056 1057 /* Disable interrupts. */ 1058 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1059 1060 for (;;) { 1061 1062 status = CSR_READ_4(sc, WB_ISR); 1063 if (status) 1064 CSR_WRITE_4(sc, WB_ISR, status); 1065 1066 if ((status & WB_INTRS) == 0) 1067 break; 1068 1069 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1070 ifp->if_ierrors++; 1071 wb_reset(sc); 1072 if (status & WB_ISR_RX_ERR) 1073 wb_fixmedia(sc); 1074 wb_init_locked(sc); 1075 continue; 1076 } 1077 1078 if (status & WB_ISR_RX_OK) 1079 wb_rxeof(sc); 1080 1081 if (status & WB_ISR_RX_IDLE) 1082 wb_rxeoc(sc); 1083 1084 if (status & WB_ISR_TX_OK) 1085 wb_txeof(sc); 1086 1087 if (status & WB_ISR_TX_NOBUF) 1088 wb_txeoc(sc); 1089 1090 if (status & WB_ISR_TX_IDLE) { 1091 wb_txeof(sc); 1092 if (sc->wb_cdata.wb_tx_head != NULL) { 1093 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1094 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1095 } 1096 } 1097 1098 if (status & WB_ISR_TX_UNDERRUN) { 1099 ifp->if_oerrors++; 1100 wb_txeof(sc); 1101 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1102 /* Jack up TX threshold */ 1103 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1104 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1105 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1106 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1107 } 1108 1109 if (status & WB_ISR_BUS_ERR) { 1110 wb_reset(sc); 1111 wb_init_locked(sc); 1112 } 1113 1114 } 1115 1116 /* Re-enable interrupts. */ 1117 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1118 1119 if (ifp->if_snd.ifq_head != NULL) { 1120 wb_start_locked(ifp); 1121 } 1122 1123 WB_UNLOCK(sc); 1124} 1125 1126static void 1127wb_tick(xsc) 1128 void *xsc; 1129{ 1130 struct wb_softc *sc; 1131 struct mii_data *mii; 1132 1133 sc = xsc; 1134 WB_LOCK_ASSERT(sc); 1135 mii = device_get_softc(sc->wb_miibus); 1136 1137 mii_tick(mii); 1138 1139 if (sc->wb_timer > 0 && --sc->wb_timer == 0) 1140 wb_watchdog(sc); 1141 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1142} 1143 1144/* 1145 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1146 * pointers to the fragment pointers. 1147 */ 1148static int 1149wb_encap(sc, c, m_head) 1150 struct wb_softc *sc; 1151 struct wb_chain *c; 1152 struct mbuf *m_head; 1153{ 1154 int frag = 0; 1155 struct wb_desc *f = NULL; 1156 int total_len; 1157 struct mbuf *m; 1158 1159 /* 1160 * Start packing the mbufs in this chain into 1161 * the fragment pointers. Stop when we run out 1162 * of fragments or hit the end of the mbuf chain. 1163 */ 1164 m = m_head; 1165 total_len = 0; 1166 1167 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1168 if (m->m_len != 0) { 1169 if (frag == WB_MAXFRAGS) 1170 break; 1171 total_len += m->m_len; 1172 f = &c->wb_ptr->wb_frag[frag]; 1173 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1174 if (frag == 0) { 1175 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1176 f->wb_status = 0; 1177 } else 1178 f->wb_status = WB_TXSTAT_OWN; 1179 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1180 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1181 frag++; 1182 } 1183 } 1184 1185 /* 1186 * Handle special case: we used up all 16 fragments, 1187 * but we have more mbufs left in the chain. Copy the 1188 * data into an mbuf cluster. Note that we don't 1189 * bother clearing the values in the other fragment 1190 * pointers/counters; it wouldn't gain us anything, 1191 * and would waste cycles. 1192 */ 1193 if (m != NULL) { 1194 struct mbuf *m_new = NULL; 1195 1196 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1197 if (m_new == NULL) 1198 return(1); 1199 if (m_head->m_pkthdr.len > MHLEN) { 1200 MCLGET(m_new, M_NOWAIT); 1201 if (!(m_new->m_flags & M_EXT)) { 1202 m_freem(m_new); 1203 return(1); 1204 } 1205 } 1206 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1207 mtod(m_new, caddr_t)); 1208 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1209 m_freem(m_head); 1210 m_head = m_new; 1211 f = &c->wb_ptr->wb_frag[0]; 1212 f->wb_status = 0; 1213 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1214 f->wb_ctl = total_len = m_new->m_len; 1215 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1216 frag = 1; 1217 } 1218 1219 if (total_len < WB_MIN_FRAMELEN) { 1220 f = &c->wb_ptr->wb_frag[frag]; 1221 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1222 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1223 f->wb_ctl |= WB_TXCTL_TLINK; 1224 f->wb_status = WB_TXSTAT_OWN; 1225 frag++; 1226 } 1227 1228 c->wb_mbuf = m_head; 1229 c->wb_lastdesc = frag - 1; 1230 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1231 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1232 1233 return(0); 1234} 1235 1236/* 1237 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1238 * to the mbuf data regions directly in the transmit lists. We also save a 1239 * copy of the pointers since the transmit list fragment pointers are 1240 * physical addresses. 1241 */ 1242 1243static void 1244wb_start(ifp) 1245 struct ifnet *ifp; 1246{ 1247 struct wb_softc *sc; 1248 1249 sc = ifp->if_softc; 1250 WB_LOCK(sc); 1251 wb_start_locked(ifp); 1252 WB_UNLOCK(sc); 1253} 1254 1255static void 1256wb_start_locked(ifp) 1257 struct ifnet *ifp; 1258{ 1259 struct wb_softc *sc; 1260 struct mbuf *m_head = NULL; 1261 struct wb_chain *cur_tx = NULL, *start_tx; 1262 1263 sc = ifp->if_softc; 1264 WB_LOCK_ASSERT(sc); 1265 1266 /* 1267 * Check for an available queue slot. If there are none, 1268 * punt. 1269 */ 1270 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1271 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1272 return; 1273 } 1274 1275 start_tx = sc->wb_cdata.wb_tx_free; 1276 1277 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1278 IF_DEQUEUE(&ifp->if_snd, m_head); 1279 if (m_head == NULL) 1280 break; 1281 1282 /* Pick a descriptor off the free list. */ 1283 cur_tx = sc->wb_cdata.wb_tx_free; 1284 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1285 1286 /* Pack the data into the descriptor. */ 1287 wb_encap(sc, cur_tx, m_head); 1288 1289 if (cur_tx != start_tx) 1290 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1291 1292 /* 1293 * If there's a BPF listener, bounce a copy of this frame 1294 * to him. 1295 */ 1296 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1297 } 1298 1299 /* 1300 * If there are no packets queued, bail. 1301 */ 1302 if (cur_tx == NULL) 1303 return; 1304 1305 /* 1306 * Place the request for the upload interrupt 1307 * in the last descriptor in the chain. This way, if 1308 * we're chaining several packets at once, we'll only 1309 * get an interrupt once for the whole chain rather than 1310 * once for each packet. 1311 */ 1312 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1313 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1314 sc->wb_cdata.wb_tx_tail = cur_tx; 1315 1316 if (sc->wb_cdata.wb_tx_head == NULL) { 1317 sc->wb_cdata.wb_tx_head = start_tx; 1318 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1319 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1320 } else { 1321 /* 1322 * We need to distinguish between the case where 1323 * the own bit is clear because the chip cleared it 1324 * and where the own bit is clear because we haven't 1325 * set it yet. The magic value WB_UNSET is just some 1326 * ramdomly chosen number which doesn't have the own 1327 * bit set. When we actually transmit the frame, the 1328 * status word will have _only_ the own bit set, so 1329 * the txeoc handler will be able to tell if it needs 1330 * to initiate another transmission to flush out pending 1331 * frames. 1332 */ 1333 WB_TXOWN(start_tx) = WB_UNSENT; 1334 } 1335 1336 /* 1337 * Set a timeout in case the chip goes out to lunch. 1338 */ 1339 sc->wb_timer = 5; 1340} 1341 1342static void 1343wb_init(xsc) 1344 void *xsc; 1345{ 1346 struct wb_softc *sc = xsc; 1347 1348 WB_LOCK(sc); 1349 wb_init_locked(sc); 1350 WB_UNLOCK(sc); 1351} 1352 1353static void 1354wb_init_locked(sc) 1355 struct wb_softc *sc; 1356{ 1357 struct ifnet *ifp = sc->wb_ifp; 1358 int i; 1359 struct mii_data *mii; 1360 1361 WB_LOCK_ASSERT(sc); 1362 mii = device_get_softc(sc->wb_miibus); 1363 1364 /* 1365 * Cancel pending I/O and free all RX/TX buffers. 1366 */ 1367 wb_stop(sc); 1368 wb_reset(sc); 1369 1370 sc->wb_txthresh = WB_TXTHRESH_INIT; 1371 1372 /* 1373 * Set cache alignment and burst length. 1374 */ 1375#ifdef foo 1376 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1377 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1378 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1379#endif 1380 1381 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1382 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1383 switch(sc->wb_cachesize) { 1384 case 32: 1385 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1386 break; 1387 case 16: 1388 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1389 break; 1390 case 8: 1391 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1392 break; 1393 case 0: 1394 default: 1395 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1396 break; 1397 } 1398 1399 /* This doesn't tend to work too well at 100Mbps. */ 1400 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1401 1402 /* Init our MAC address */ 1403 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1404 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]); 1405 } 1406 1407 /* Init circular RX list. */ 1408 if (wb_list_rx_init(sc) == ENOBUFS) { 1409 device_printf(sc->wb_dev, 1410 "initialization failed: no memory for rx buffers\n"); 1411 wb_stop(sc); 1412 return; 1413 } 1414 1415 /* Init TX descriptors. */ 1416 wb_list_tx_init(sc); 1417 1418 /* If we want promiscuous mode, set the allframes bit. */ 1419 if (ifp->if_flags & IFF_PROMISC) { 1420 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1421 } else { 1422 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1423 } 1424 1425 /* 1426 * Set capture broadcast bit to capture broadcast frames. 1427 */ 1428 if (ifp->if_flags & IFF_BROADCAST) { 1429 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1430 } else { 1431 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1432 } 1433 1434 /* 1435 * Program the multicast filter, if necessary. 1436 */ 1437 wb_setmulti(sc); 1438 1439 /* 1440 * Load the address of the RX list. 1441 */ 1442 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1443 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1444 1445 /* 1446 * Enable interrupts. 1447 */ 1448 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1449 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1450 1451 /* Enable receiver and transmitter. */ 1452 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1453 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1454 1455 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1456 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1457 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1458 1459 mii_mediachg(mii); 1460 1461 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1462 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1463 1464 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1465} 1466 1467/* 1468 * Set media options. 1469 */ 1470static int 1471wb_ifmedia_upd(ifp) 1472 struct ifnet *ifp; 1473{ 1474 struct wb_softc *sc; 1475 1476 sc = ifp->if_softc; 1477 1478 WB_LOCK(sc); 1479 if (ifp->if_flags & IFF_UP) 1480 wb_init_locked(sc); 1481 WB_UNLOCK(sc); 1482 1483 return(0); 1484} 1485 1486/* 1487 * Report current media status. 1488 */ 1489static void 1490wb_ifmedia_sts(ifp, ifmr) 1491 struct ifnet *ifp; 1492 struct ifmediareq *ifmr; 1493{ 1494 struct wb_softc *sc; 1495 struct mii_data *mii; 1496 1497 sc = ifp->if_softc; 1498 1499 WB_LOCK(sc); 1500 mii = device_get_softc(sc->wb_miibus); 1501 1502 mii_pollstat(mii); 1503 ifmr->ifm_active = mii->mii_media_active; 1504 ifmr->ifm_status = mii->mii_media_status; 1505 WB_UNLOCK(sc); 1506} 1507 1508static int 1509wb_ioctl(ifp, command, data) 1510 struct ifnet *ifp; 1511 u_long command; 1512 caddr_t data; 1513{ 1514 struct wb_softc *sc = ifp->if_softc; 1515 struct mii_data *mii; 1516 struct ifreq *ifr = (struct ifreq *) data; 1517 int error = 0; 1518 1519 switch(command) { 1520 case SIOCSIFFLAGS: 1521 WB_LOCK(sc); 1522 if (ifp->if_flags & IFF_UP) { 1523 wb_init_locked(sc); 1524 } else { 1525 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1526 wb_stop(sc); 1527 } 1528 WB_UNLOCK(sc); 1529 error = 0; 1530 break; 1531 case SIOCADDMULTI: 1532 case SIOCDELMULTI: 1533 WB_LOCK(sc); 1534 wb_setmulti(sc); 1535 WB_UNLOCK(sc); 1536 error = 0; 1537 break; 1538 case SIOCGIFMEDIA: 1539 case SIOCSIFMEDIA: 1540 mii = device_get_softc(sc->wb_miibus); 1541 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1542 break; 1543 default: 1544 error = ether_ioctl(ifp, command, data); 1545 break; 1546 } 1547 1548 return(error); 1549} 1550 1551static void 1552wb_watchdog(sc) 1553 struct wb_softc *sc; 1554{ 1555 struct ifnet *ifp; 1556 1557 WB_LOCK_ASSERT(sc); 1558 ifp = sc->wb_ifp; 1559 ifp->if_oerrors++; 1560 if_printf(ifp, "watchdog timeout\n"); 1561#ifdef foo 1562 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1563 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1564#endif 1565 wb_stop(sc); 1566 wb_reset(sc); 1567 wb_init_locked(sc); 1568 1569 if (ifp->if_snd.ifq_head != NULL) 1570 wb_start_locked(ifp); 1571} 1572 1573/* 1574 * Stop the adapter and free any mbufs allocated to the 1575 * RX and TX lists. 1576 */ 1577static void 1578wb_stop(sc) 1579 struct wb_softc *sc; 1580{ 1581 register int i; 1582 struct ifnet *ifp; 1583 1584 WB_LOCK_ASSERT(sc); 1585 ifp = sc->wb_ifp; 1586 sc->wb_timer = 0; 1587 1588 callout_stop(&sc->wb_stat_callout); 1589 1590 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1591 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1592 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1593 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1594 1595 /* 1596 * Free data in the RX lists. 1597 */ 1598 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1599 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1600 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1601 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1602 } 1603 } 1604 bzero((char *)&sc->wb_ldata->wb_rx_list, 1605 sizeof(sc->wb_ldata->wb_rx_list)); 1606 1607 /* 1608 * Free the TX list buffers. 1609 */ 1610 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1611 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1612 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1613 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1614 } 1615 } 1616 1617 bzero((char *)&sc->wb_ldata->wb_tx_list, 1618 sizeof(sc->wb_ldata->wb_tx_list)); 1619 1620 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1621} 1622 1623/* 1624 * Stop all chip I/O so that the kernel's probe routines don't 1625 * get confused by errant DMAs when rebooting. 1626 */ 1627static int 1628wb_shutdown(dev) 1629 device_t dev; 1630{ 1631 struct wb_softc *sc; 1632 1633 sc = device_get_softc(dev); 1634 1635 WB_LOCK(sc); 1636 wb_stop(sc); 1637 WB_UNLOCK(sc); 1638 1639 return (0); 1640} 1641