1139825Simp/*- 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD$"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * Winbond fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 4041502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 4141502Swpaul * Winbond itself and some made by Linksys. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 4741502Swpaul/* 4841502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4941502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 5041502Swpaul * one major difference which is that while the registers do many of 5141502Swpaul * the same things as a tulip adapter, the offsets are different: where 5241502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5341502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5441502Swpaul * programmed differently. 5541502Swpaul * 5641502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5741502Swpaul * a status word, a control word and 32-bit areas that can either be used 5841502Swpaul * to point to two external data blocks, or to point to a single block 5941502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 6041502Swpaul * together in blocks to form fixed length rings or can be chained 6141502Swpaul * together in linked lists. A single packet may be spread out over 6241502Swpaul * several descriptors if necessary. 6341502Swpaul * 6441502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6541502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6641502Swpaul * to hold an entire packet. The link list is looped back to created a 6741502Swpaul * closed ring. 6841502Swpaul * 6941502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 7041502Swpaul * which each contain several individual descriptors linked toghether. 7141502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7241502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7341502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7441502Swpaul * drivers. 7541502Swpaul * 7641502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7741502Swpaul * The sample boards I have all use a Davicom PHY. 7841502Swpaul * 7941502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 8041502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 8141502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8241502Swpaul * I have no idea what he's on about: transmit performance with all 8341502Swpaul * three of my test boards seems fine. 8441502Swpaul */ 8541502Swpaul 8641502Swpaul#include <sys/param.h> 8741502Swpaul#include <sys/systm.h> 8841502Swpaul#include <sys/sockio.h> 8941502Swpaul#include <sys/mbuf.h> 9041502Swpaul#include <sys/malloc.h> 91129878Sphk#include <sys/module.h> 9241502Swpaul#include <sys/kernel.h> 9341502Swpaul#include <sys/socket.h> 9450675Swpaul#include <sys/queue.h> 9541502Swpaul 9641502Swpaul#include <net/if.h> 9741502Swpaul#include <net/if_arp.h> 9841502Swpaul#include <net/ethernet.h> 9941502Swpaul#include <net/if_dl.h> 10041502Swpaul#include <net/if_media.h> 101147256Sbrooks#include <net/if_types.h> 10241502Swpaul 10341502Swpaul#include <net/bpf.h> 10441502Swpaul 10541502Swpaul#include <vm/vm.h> /* for vtophys */ 10641502Swpaul#include <vm/pmap.h> /* for vtophys */ 10741502Swpaul#include <machine/bus.h> 10849611Swpaul#include <machine/resource.h> 10949611Swpaul#include <sys/bus.h> 11049611Swpaul#include <sys/rman.h> 11141502Swpaul 112119288Simp#include <dev/pci/pcireg.h> 113119288Simp#include <dev/pci/pcivar.h> 11441502Swpaul 11550675Swpaul#include <dev/mii/mii.h> 116227277Smarius#include <dev/mii/mii_bitbang.h> 11750675Swpaul#include <dev/mii/miivar.h> 11850675Swpaul 119151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 12050675Swpaul#include "miibus_if.h" 12150675Swpaul 12241502Swpaul#define WB_USEIOSPACE 12341502Swpaul 124181741Simp#include <dev/wb/if_wbreg.h> 12541502Swpaul 126113506SmdoddMODULE_DEPEND(wb, pci, 1, 1, 1); 127113506SmdoddMODULE_DEPEND(wb, ether, 1, 1, 1); 12859758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 12959758Speter 13041502Swpaul/* 13141502Swpaul * Various supported device vendors/types and their names. 13241502Swpaul */ 133242908Sdimstatic const struct wb_type wb_devs[] = { 13441502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13541502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13641502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13741502Swpaul "Compex RL100-ATX 10/100baseTX" }, 13841502Swpaul { 0, 0, NULL } 13941502Swpaul}; 14041502Swpaul 141142407Simpstatic int wb_probe(device_t); 142142407Simpstatic int wb_attach(device_t); 143142407Simpstatic int wb_detach(device_t); 14441502Swpaul 145142407Simpstatic void wb_bfree(void *addr, void *args); 146142407Simpstatic int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 147142407Simp struct mbuf *); 148142407Simpstatic int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 14941502Swpaul 150142407Simpstatic void wb_rxeof(struct wb_softc *); 151142407Simpstatic void wb_rxeoc(struct wb_softc *); 152142407Simpstatic void wb_txeof(struct wb_softc *); 153142407Simpstatic void wb_txeoc(struct wb_softc *); 154142407Simpstatic void wb_intr(void *); 155142407Simpstatic void wb_tick(void *); 156142407Simpstatic void wb_start(struct ifnet *); 157151774Sjhbstatic void wb_start_locked(struct ifnet *); 158142407Simpstatic int wb_ioctl(struct ifnet *, u_long, caddr_t); 159142407Simpstatic void wb_init(void *); 160151774Sjhbstatic void wb_init_locked(struct wb_softc *); 161142407Simpstatic void wb_stop(struct wb_softc *); 162199560Sjhbstatic void wb_watchdog(struct wb_softc *); 163194023Savgstatic int wb_shutdown(device_t); 164142407Simpstatic int wb_ifmedia_upd(struct ifnet *); 165142407Simpstatic void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 16641502Swpaul 167142407Simpstatic void wb_eeprom_putbyte(struct wb_softc *, int); 168142407Simpstatic void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 169142407Simpstatic void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 17041502Swpaul 171142407Simpstatic void wb_setcfg(struct wb_softc *, u_int32_t); 172142407Simpstatic void wb_setmulti(struct wb_softc *); 173142407Simpstatic void wb_reset(struct wb_softc *); 174142407Simpstatic void wb_fixmedia(struct wb_softc *); 175142407Simpstatic int wb_list_rx_init(struct wb_softc *); 176142407Simpstatic int wb_list_tx_init(struct wb_softc *); 17741502Swpaul 178142407Simpstatic int wb_miibus_readreg(device_t, int, int); 179142407Simpstatic int wb_miibus_writereg(device_t, int, int, int); 180142407Simpstatic void wb_miibus_statchg(device_t); 18150675Swpaul 182227277Smarius/* 183227277Smarius * MII bit-bang glue 184227277Smarius */ 185227277Smariusstatic uint32_t wb_mii_bitbang_read(device_t); 186227277Smariusstatic void wb_mii_bitbang_write(device_t, uint32_t); 187227277Smarius 188227277Smariusstatic const struct mii_bitbang_ops wb_mii_bitbang_ops = { 189227277Smarius wb_mii_bitbang_read, 190227277Smarius wb_mii_bitbang_write, 191227277Smarius { 192227277Smarius WB_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 193227277Smarius WB_SIO_MII_DATAIN, /* MII_BIT_MDI */ 194227277Smarius WB_SIO_MII_CLK, /* MII_BIT_MDC */ 195227277Smarius WB_SIO_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 196227277Smarius 0, /* MII_BIT_DIR_PHY_HOST */ 197227277Smarius } 198227277Smarius}; 199227277Smarius 20049611Swpaul#ifdef WB_USEIOSPACE 20149611Swpaul#define WB_RES SYS_RES_IOPORT 20249611Swpaul#define WB_RID WB_PCI_LOIO 20349611Swpaul#else 20449611Swpaul#define WB_RES SYS_RES_MEMORY 20549611Swpaul#define WB_RID WB_PCI_LOMEM 20649611Swpaul#endif 20749611Swpaul 20849611Swpaulstatic device_method_t wb_methods[] = { 20949611Swpaul /* Device interface */ 21049611Swpaul DEVMETHOD(device_probe, wb_probe), 21149611Swpaul DEVMETHOD(device_attach, wb_attach), 21249611Swpaul DEVMETHOD(device_detach, wb_detach), 21349611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 21450675Swpaul 21550675Swpaul /* MII interface */ 21650675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 21750675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 21850675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 219229093Shselasky 220229093Shselasky DEVMETHOD_END 22149611Swpaul}; 22249611Swpaul 22349611Swpaulstatic driver_t wb_driver = { 22451455Swpaul "wb", 22549611Swpaul wb_methods, 22649611Swpaul sizeof(struct wb_softc) 22749611Swpaul}; 22849611Swpaul 22949611Swpaulstatic devclass_t wb_devclass; 23049611Swpaul 231113506SmdoddDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 23251473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 23349611Swpaul 23441502Swpaul#define WB_SETBIT(sc, reg, x) \ 23541502Swpaul CSR_WRITE_4(sc, reg, \ 236105221Sphk CSR_READ_4(sc, reg) | (x)) 23741502Swpaul 23841502Swpaul#define WB_CLRBIT(sc, reg, x) \ 23941502Swpaul CSR_WRITE_4(sc, reg, \ 240105221Sphk CSR_READ_4(sc, reg) & ~(x)) 24141502Swpaul 24241502Swpaul#define SIO_SET(x) \ 24341502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 244105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 24541502Swpaul 24641502Swpaul#define SIO_CLR(x) \ 24741502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 248105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 24941502Swpaul 25041502Swpaul/* 25141502Swpaul * Send a read command and address to the EEPROM, check for ACK. 25241502Swpaul */ 253102336Salfredstatic void 254102336Salfredwb_eeprom_putbyte(sc, addr) 25541502Swpaul struct wb_softc *sc; 25642718Swpaul int addr; 25741502Swpaul{ 25841502Swpaul register int d, i; 25941502Swpaul 26041502Swpaul d = addr | WB_EECMD_READ; 26141502Swpaul 26241502Swpaul /* 26341502Swpaul * Feed in each bit and stobe the clock. 26441502Swpaul */ 26541502Swpaul for (i = 0x400; i; i >>= 1) { 26641502Swpaul if (d & i) { 26741502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 26841502Swpaul } else { 26941502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 27041502Swpaul } 27141502Swpaul DELAY(100); 27241502Swpaul SIO_SET(WB_SIO_EE_CLK); 27341502Swpaul DELAY(150); 27441502Swpaul SIO_CLR(WB_SIO_EE_CLK); 27541502Swpaul DELAY(100); 27641502Swpaul } 27741502Swpaul} 27841502Swpaul 27941502Swpaul/* 28041502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 28141502Swpaul */ 282102336Salfredstatic void 283102336Salfredwb_eeprom_getword(sc, addr, dest) 28441502Swpaul struct wb_softc *sc; 28542718Swpaul int addr; 28641502Swpaul u_int16_t *dest; 28741502Swpaul{ 28841502Swpaul register int i; 28941502Swpaul u_int16_t word = 0; 29041502Swpaul 29141502Swpaul /* Enter EEPROM access mode. */ 29241502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29341502Swpaul 29441502Swpaul /* 29541502Swpaul * Send address of word we want to read. 29641502Swpaul */ 29741502Swpaul wb_eeprom_putbyte(sc, addr); 29841502Swpaul 29941502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 30041502Swpaul 30141502Swpaul /* 30241502Swpaul * Start reading bits from EEPROM. 30341502Swpaul */ 30441502Swpaul for (i = 0x8000; i; i >>= 1) { 30541502Swpaul SIO_SET(WB_SIO_EE_CLK); 30641502Swpaul DELAY(100); 30741502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30841502Swpaul word |= i; 30941502Swpaul SIO_CLR(WB_SIO_EE_CLK); 31041502Swpaul DELAY(100); 31141502Swpaul } 31241502Swpaul 31341502Swpaul /* Turn off EEPROM access mode. */ 31441502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 31541502Swpaul 31641502Swpaul *dest = word; 31741502Swpaul} 31841502Swpaul 31941502Swpaul/* 32041502Swpaul * Read a sequence of words from the EEPROM. 32141502Swpaul */ 322102336Salfredstatic void 323102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 32441502Swpaul struct wb_softc *sc; 32541502Swpaul caddr_t dest; 32641502Swpaul int off; 32741502Swpaul int cnt; 32841502Swpaul int swap; 32941502Swpaul{ 33041502Swpaul int i; 33141502Swpaul u_int16_t word = 0, *ptr; 33241502Swpaul 33341502Swpaul for (i = 0; i < cnt; i++) { 33441502Swpaul wb_eeprom_getword(sc, off + i, &word); 33541502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33641502Swpaul if (swap) 33741502Swpaul *ptr = ntohs(word); 33841502Swpaul else 33941502Swpaul *ptr = word; 34041502Swpaul } 34141502Swpaul} 34241502Swpaul 34341502Swpaul/* 344227277Smarius * Read the MII serial port for the MII bit-bang module. 34541502Swpaul */ 346227277Smariusstatic uint32_t 347227277Smariuswb_mii_bitbang_read(device_t dev) 34841502Swpaul{ 349227277Smarius struct wb_softc *sc; 350227277Smarius uint32_t val; 35141502Swpaul 352227277Smarius sc = device_get_softc(dev); 35341502Swpaul 354227277Smarius val = CSR_READ_4(sc, WB_SIO); 355227277Smarius CSR_BARRIER(sc, WB_SIO, 4, 356227277Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 35741502Swpaul 358227277Smarius return (val); 35941502Swpaul} 36041502Swpaul 36141502Swpaul/* 362227277Smarius * Write the MII serial port for the MII bit-bang module. 36341502Swpaul */ 364102336Salfredstatic void 365227277Smariuswb_mii_bitbang_write(device_t dev, uint32_t val) 36641502Swpaul{ 367227277Smarius struct wb_softc *sc; 36841502Swpaul 369227277Smarius sc = device_get_softc(dev); 37041502Swpaul 371227277Smarius CSR_WRITE_4(sc, WB_SIO, val); 372227277Smarius CSR_BARRIER(sc, WB_SIO, 4, 373227277Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 37441502Swpaul} 37541502Swpaul 376102336Salfredstatic int 377102336Salfredwb_miibus_readreg(dev, phy, reg) 37850675Swpaul device_t dev; 37950675Swpaul int phy, reg; 38050675Swpaul{ 38141502Swpaul 382227277Smarius return (mii_bitbang_readreg(dev, &wb_mii_bitbang_ops, phy, reg)); 38341502Swpaul} 38441502Swpaul 385102336Salfredstatic int 386102336Salfredwb_miibus_writereg(dev, phy, reg, data) 38750675Swpaul device_t dev; 38850675Swpaul int phy, reg, data; 38950675Swpaul{ 39041502Swpaul 391227277Smarius mii_bitbang_writereg(dev, &wb_mii_bitbang_ops, phy, reg, data); 39250675Swpaul 39350675Swpaul return(0); 39450675Swpaul} 39550675Swpaul 396102336Salfredstatic void 397102336Salfredwb_miibus_statchg(dev) 39850675Swpaul device_t dev; 39950675Swpaul{ 40050675Swpaul struct wb_softc *sc; 40150675Swpaul struct mii_data *mii; 40250675Swpaul 40350675Swpaul sc = device_get_softc(dev); 40450675Swpaul mii = device_get_softc(sc->wb_miibus); 40550675Swpaul wb_setcfg(sc, mii->mii_media_active); 40641502Swpaul} 40741502Swpaul 40841502Swpaul/* 40941502Swpaul * Program the 64-bit multicast hash filter. 41041502Swpaul */ 411102336Salfredstatic void 412102336Salfredwb_setmulti(sc) 41341502Swpaul struct wb_softc *sc; 41441502Swpaul{ 41541502Swpaul struct ifnet *ifp; 41641502Swpaul int h = 0; 41741502Swpaul u_int32_t hashes[2] = { 0, 0 }; 41841502Swpaul struct ifmultiaddr *ifma; 41941502Swpaul u_int32_t rxfilt; 42041502Swpaul int mcnt = 0; 42141502Swpaul 422147256Sbrooks ifp = sc->wb_ifp; 42341502Swpaul 42441502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 42541502Swpaul 42641502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 42741502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 42841502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 42941502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 43041502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 43141502Swpaul return; 43241502Swpaul } 43341502Swpaul 43441502Swpaul /* first, zot all the existing hash bits */ 43541502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 43641502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 43741502Swpaul 43841502Swpaul /* now program new ones */ 439195049Srwatson if_maddr_rlock(ifp); 44072084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 44141502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 44241502Swpaul continue; 443130270Snaddy h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 444130270Snaddy ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 44541502Swpaul if (h < 32) 44641502Swpaul hashes[0] |= (1 << h); 44741502Swpaul else 44841502Swpaul hashes[1] |= (1 << (h - 32)); 44941502Swpaul mcnt++; 45041502Swpaul } 451195049Srwatson if_maddr_runlock(ifp); 45241502Swpaul 45341502Swpaul if (mcnt) 45441502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 45541502Swpaul else 45641502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 45741502Swpaul 45841502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 45941502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 46041502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 46141502Swpaul} 46241502Swpaul 46341502Swpaul/* 46441502Swpaul * The Winbond manual states that in order to fiddle with the 46541502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 46641502Swpaul * first have to put the transmit and/or receive logic in the idle state. 46741502Swpaul */ 468102336Salfredstatic void 469102336Salfredwb_setcfg(sc, media) 47041502Swpaul struct wb_softc *sc; 47150675Swpaul u_int32_t media; 47241502Swpaul{ 47341502Swpaul int i, restart = 0; 47441502Swpaul 47541502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 47641502Swpaul restart = 1; 47741502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 47841502Swpaul 47941502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 48041502Swpaul DELAY(10); 48141502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 48241502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 48341502Swpaul break; 48441502Swpaul } 48541502Swpaul 48641502Swpaul if (i == WB_TIMEOUT) 487162315Sglebius device_printf(sc->wb_dev, 488149677Sjhb "failed to force tx and rx to idle state\n"); 48941502Swpaul } 49041502Swpaul 49150675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 49250675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 49350675Swpaul else 49441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 49541502Swpaul 49650675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 49741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 49841502Swpaul else 49941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 50041502Swpaul 50141502Swpaul if (restart) 50241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 50341502Swpaul} 50441502Swpaul 505102336Salfredstatic void 506102336Salfredwb_reset(sc) 50741502Swpaul struct wb_softc *sc; 50841502Swpaul{ 50941502Swpaul register int i; 51050675Swpaul struct mii_data *mii; 511221407Smarius struct mii_softc *miisc; 51241502Swpaul 51350675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 51450675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 51550675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 51650675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 51750675Swpaul 51841502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 51950675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 52041502Swpaul 52141502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 52241502Swpaul DELAY(10); 52341502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 52441502Swpaul break; 52541502Swpaul } 52641502Swpaul if (i == WB_TIMEOUT) 527162315Sglebius device_printf(sc->wb_dev, "reset never completed!\n"); 52841502Swpaul 52941502Swpaul /* Wait a little while for the chip to get its brains in order. */ 53041502Swpaul DELAY(1000); 53141502Swpaul 53250675Swpaul if (sc->wb_miibus == NULL) 53350675Swpaul return; 53441502Swpaul 53550675Swpaul mii = device_get_softc(sc->wb_miibus); 536221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 537221407Smarius PHY_RESET(miisc); 53841502Swpaul} 53941502Swpaul 540102336Salfredstatic void 541102336Salfredwb_fixmedia(sc) 54250675Swpaul struct wb_softc *sc; 54350675Swpaul{ 54450675Swpaul struct mii_data *mii = NULL; 54550675Swpaul struct ifnet *ifp; 54650675Swpaul u_int32_t media; 54750675Swpaul 54850675Swpaul mii = device_get_softc(sc->wb_miibus); 549147256Sbrooks ifp = sc->wb_ifp; 55050675Swpaul 55150675Swpaul mii_pollstat(mii); 55250675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 55350675Swpaul media = mii->mii_media_active & ~IFM_10_T; 55450675Swpaul media |= IFM_100_TX; 55550675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 55650675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 55750675Swpaul media |= IFM_10_T; 55850675Swpaul } else 55950675Swpaul return; 56050675Swpaul 56150675Swpaul ifmedia_set(&mii->mii_media, media); 56250675Swpaul} 56350675Swpaul 56441502Swpaul/* 56541502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 56641502Swpaul * IDs against our list and return a device name if we find a match. 56741502Swpaul */ 568102336Salfredstatic int 569102336Salfredwb_probe(dev) 57049611Swpaul device_t dev; 57141502Swpaul{ 572227277Smarius const struct wb_type *t; 57341502Swpaul 57441502Swpaul t = wb_devs; 57541502Swpaul 57641502Swpaul while(t->wb_name != NULL) { 57749611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 57849611Swpaul (pci_get_device(dev) == t->wb_did)) { 57949611Swpaul device_set_desc(dev, t->wb_name); 580142398Simp return (BUS_PROBE_DEFAULT); 58141502Swpaul } 58241502Swpaul t++; 58341502Swpaul } 58441502Swpaul 58549611Swpaul return(ENXIO); 58641502Swpaul} 58741502Swpaul 58841502Swpaul/* 58941502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 59041502Swpaul * setup and ethernet/BPF attach. 59141502Swpaul */ 592102336Salfredstatic int 593102336Salfredwb_attach(dev) 59449611Swpaul device_t dev; 59541502Swpaul{ 59641502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 59741502Swpaul struct wb_softc *sc; 59841502Swpaul struct ifnet *ifp; 599149677Sjhb int error = 0, rid; 60041502Swpaul 60149611Swpaul sc = device_get_softc(dev); 602162315Sglebius sc->wb_dev = dev; 60341502Swpaul 60493818Sjhb mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 605151774Sjhb MTX_DEF); 606151774Sjhb callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0); 607151774Sjhb 60841502Swpaul /* 60941502Swpaul * Map control/status registers. 61041502Swpaul */ 61172813Swpaul pci_enable_busmaster(dev); 61241502Swpaul 61349611Swpaul rid = WB_RID; 614127135Snjl sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 61549611Swpaul 61649611Swpaul if (sc->wb_res == NULL) { 617149677Sjhb device_printf(dev, "couldn't map ports/memory\n"); 61849611Swpaul error = ENXIO; 61941502Swpaul goto fail; 62041502Swpaul } 62141502Swpaul 62241502Swpaul /* Allocate interrupt */ 62349611Swpaul rid = 0; 624127135Snjl sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 62549611Swpaul RF_SHAREABLE | RF_ACTIVE); 62649611Swpaul 62749611Swpaul if (sc->wb_irq == NULL) { 628149677Sjhb device_printf(dev, "couldn't map interrupt\n"); 62949611Swpaul error = ENXIO; 63041502Swpaul goto fail; 63141502Swpaul } 63241502Swpaul 63350675Swpaul /* Save the cache line size. */ 63450675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 63550675Swpaul 63641502Swpaul /* Reset the adapter. */ 63741502Swpaul wb_reset(sc); 63841502Swpaul 63941502Swpaul /* 64041502Swpaul * Get station address from the EEPROM. 64141502Swpaul */ 64241502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 64341502Swpaul 64450675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 64551657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 64650675Swpaul 64750675Swpaul if (sc->wb_ldata == NULL) { 648149677Sjhb device_printf(dev, "no memory for list buffers!\n"); 64949611Swpaul error = ENXIO; 65049611Swpaul goto fail; 65141502Swpaul } 65241502Swpaul 65341502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 65441502Swpaul 655147256Sbrooks ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 656147256Sbrooks if (ifp == NULL) { 657149677Sjhb device_printf(dev, "can not if_alloc()\n"); 658147256Sbrooks error = ENOSPC; 659147256Sbrooks goto fail; 660147256Sbrooks } 66141502Swpaul ifp->if_softc = sc; 662121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 66341502Swpaul ifp->if_mtu = ETHERMTU; 664151774Sjhb ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 66541502Swpaul ifp->if_ioctl = wb_ioctl; 66641502Swpaul ifp->if_start = wb_start; 66741502Swpaul ifp->if_init = wb_init; 66843515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 66941502Swpaul 67050675Swpaul /* 67150675Swpaul * Do MII setup. 67250675Swpaul */ 673213894Smarius error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd, 674213894Smarius wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 675214913Smarius if (error != 0) { 676213894Smarius device_printf(dev, "attaching PHYs failed\n"); 67741502Swpaul goto fail; 67841502Swpaul } 67941502Swpaul 68041502Swpaul /* 68163090Sarchie * Call MI attach routine. 68241502Swpaul */ 683106936Ssam ether_ifattach(ifp, eaddr); 68441502Swpaul 685113609Snjl /* Hook interrupt last to avoid having to lock softc */ 686151774Sjhb error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE, 687166901Spiso NULL, wb_intr, sc, &sc->wb_intrhand); 688112872Snjl 689112872Snjl if (error) { 690149677Sjhb device_printf(dev, "couldn't set up irq\n"); 691113609Snjl ether_ifdetach(ifp); 692112872Snjl goto fail; 693112872Snjl } 694112872Snjl 69541502Swpaulfail: 69650675Swpaul if (error) 697112872Snjl wb_detach(dev); 69850675Swpaul 69949611Swpaul return(error); 70041502Swpaul} 70141502Swpaul 702113609Snjl/* 703113609Snjl * Shutdown hardware and free up resources. This can be called any 704113609Snjl * time after the mutex has been initialized. It is called in both 705113609Snjl * the error case in attach and the normal detach case so it needs 706113609Snjl * to be careful about only freeing resources that have actually been 707113609Snjl * allocated. 708113609Snjl */ 709102336Salfredstatic int 710102336Salfredwb_detach(dev) 71149611Swpaul device_t dev; 71249611Swpaul{ 71349611Swpaul struct wb_softc *sc; 71449611Swpaul struct ifnet *ifp; 71549611Swpaul 71649611Swpaul sc = device_get_softc(dev); 717112880Sjhb KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 718147256Sbrooks ifp = sc->wb_ifp; 71949611Swpaul 720113609Snjl /* 721113609Snjl * Delete any miibus and phy devices attached to this interface. 722113609Snjl * This should only be done if attach succeeded. 723113609Snjl */ 724113812Simp if (device_is_attached(dev)) { 725199560Sjhb ether_ifdetach(ifp); 726151774Sjhb WB_LOCK(sc); 727113609Snjl wb_stop(sc); 728151774Sjhb WB_UNLOCK(sc); 729151774Sjhb callout_drain(&sc->wb_stat_callout); 730150213Sru } 731113609Snjl if (sc->wb_miibus) 732112872Snjl device_delete_child(dev, sc->wb_miibus); 733113609Snjl bus_generic_detach(dev); 73450675Swpaul 735112872Snjl if (sc->wb_intrhand) 736112872Snjl bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 737112872Snjl if (sc->wb_irq) 738112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 739112872Snjl if (sc->wb_res) 740112872Snjl bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 74149611Swpaul 742151297Sru if (ifp) 743151297Sru if_free(ifp); 744151297Sru 745112872Snjl if (sc->wb_ldata) { 746112872Snjl contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 747112872Snjl M_DEVBUF); 748112872Snjl } 74949611Swpaul 75067087Swpaul mtx_destroy(&sc->wb_mtx); 75149611Swpaul 75249611Swpaul return(0); 75349611Swpaul} 75449611Swpaul 75541502Swpaul/* 75641502Swpaul * Initialize the transmit descriptors. 75741502Swpaul */ 758102336Salfredstatic int 759102336Salfredwb_list_tx_init(sc) 76041502Swpaul struct wb_softc *sc; 76141502Swpaul{ 76241502Swpaul struct wb_chain_data *cd; 76341502Swpaul struct wb_list_data *ld; 76441502Swpaul int i; 76541502Swpaul 76641502Swpaul cd = &sc->wb_cdata; 76741502Swpaul ld = sc->wb_ldata; 76841502Swpaul 76941502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 77041502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 77141502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 77241502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 77341502Swpaul &cd->wb_tx_chain[0]; 77441502Swpaul } else { 77541502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 77641502Swpaul &cd->wb_tx_chain[i + 1]; 77741502Swpaul } 77841502Swpaul } 77941502Swpaul 78041502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 78141502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 78241502Swpaul 78341502Swpaul return(0); 78441502Swpaul} 78541502Swpaul 78641502Swpaul 78741502Swpaul/* 78841502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 78941502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 79041502Swpaul * points back to the first. 79141502Swpaul */ 792102336Salfredstatic int 793102336Salfredwb_list_rx_init(sc) 79441502Swpaul struct wb_softc *sc; 79541502Swpaul{ 79641502Swpaul struct wb_chain_data *cd; 79741502Swpaul struct wb_list_data *ld; 79841502Swpaul int i; 79941502Swpaul 80041502Swpaul cd = &sc->wb_cdata; 80141502Swpaul ld = sc->wb_ldata; 80241502Swpaul 80341502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 80441502Swpaul cd->wb_rx_chain[i].wb_ptr = 80541502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 80650675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 80748745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 80841502Swpaul return(ENOBUFS); 80941502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 81041502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 81141502Swpaul ld->wb_rx_list[i].wb_next = 81241502Swpaul vtophys(&ld->wb_rx_list[0]); 81341502Swpaul } else { 81441502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 81541502Swpaul &cd->wb_rx_chain[i + 1]; 81641502Swpaul ld->wb_rx_list[i].wb_next = 81741502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 81841502Swpaul } 81941502Swpaul } 82041502Swpaul 82141502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 82241502Swpaul 82341502Swpaul return(0); 82441502Swpaul} 82541502Swpaul 826102336Salfredstatic void 827102336Salfredwb_bfree(buf, args) 82898995Salfred void *buf; 82964837Sdwmalone void *args; 83050675Swpaul{ 831227277Smarius 83250675Swpaul} 83350675Swpaul 83441502Swpaul/* 83541502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 83641502Swpaul */ 837102336Salfredstatic int 838102336Salfredwb_newbuf(sc, c, m) 83941502Swpaul struct wb_softc *sc; 84041502Swpaul struct wb_chain_onefrag *c; 84148745Swpaul struct mbuf *m; 84241502Swpaul{ 84341502Swpaul struct mbuf *m_new = NULL; 84441502Swpaul 84548745Swpaul if (m == NULL) { 846248078Smarius MGETHDR(m_new, M_NOWAIT, MT_DATA); 84787846Sluigi if (m_new == NULL) 84848745Swpaul return(ENOBUFS); 84964837Sdwmalone m_new->m_data = c->wb_buf; 85064837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 851175872Sphk MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf, 852175872Sphk NULL, 0, EXT_NET_DRV); 85348745Swpaul } else { 85448745Swpaul m_new = m; 85550675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 85648745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 85741502Swpaul } 85841502Swpaul 85948745Swpaul m_adj(m_new, sizeof(u_int64_t)); 86048745Swpaul 86141502Swpaul c->wb_mbuf = m_new; 86241502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 86350675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 86441502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 86541502Swpaul 86641502Swpaul return(0); 86741502Swpaul} 86841502Swpaul 86941502Swpaul/* 87041502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 87141502Swpaul * the higher level protocols. 87241502Swpaul */ 873102336Salfredstatic void 874102336Salfredwb_rxeof(sc) 87541502Swpaul struct wb_softc *sc; 87641502Swpaul{ 87750675Swpaul struct mbuf *m = NULL; 87841502Swpaul struct ifnet *ifp; 87941502Swpaul struct wb_chain_onefrag *cur_rx; 88041502Swpaul int total_len = 0; 88141502Swpaul u_int32_t rxstat; 88241502Swpaul 883122689Ssam WB_LOCK_ASSERT(sc); 884122689Ssam 885147256Sbrooks ifp = sc->wb_ifp; 88641502Swpaul 88741502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 88841502Swpaul WB_RXSTAT_OWN)) { 88948745Swpaul struct mbuf *m0 = NULL; 89048745Swpaul 89141502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 89241502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 89350675Swpaul 89448745Swpaul m = cur_rx->wb_mbuf; 89541502Swpaul 89650675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 89750675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 89850675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 89950675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 90050675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 90141502Swpaul ifp->if_ierrors++; 90250675Swpaul wb_newbuf(sc, cur_rx, m); 903162315Sglebius device_printf(sc->wb_dev, 904162315Sglebius "receiver babbling: possible chip bug," 905162315Sglebius " forcing reset\n"); 90650675Swpaul wb_fixmedia(sc); 90750675Swpaul wb_reset(sc); 908151774Sjhb wb_init_locked(sc); 90941502Swpaul return; 91041502Swpaul } 91141502Swpaul 91242718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 91342718Swpaul ifp->if_ierrors++; 91448745Swpaul wb_newbuf(sc, cur_rx, m); 91550675Swpaul break; 91642718Swpaul } 91742718Swpaul 91841502Swpaul /* No errors; receive the packet. */ 91941502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 92041502Swpaul 92141502Swpaul /* 92241934Swpaul * XXX The Winbond chip includes the CRC with every 92341934Swpaul * received frame, and there's no way to turn this 92441934Swpaul * behavior off (at least, I can't find anything in 92541934Swpaul * the manual that explains how to do it) so we have 92641934Swpaul * to trim off the CRC manually. 92741934Swpaul */ 92841934Swpaul total_len -= ETHER_CRC_LEN; 92941934Swpaul 93078508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 93178508Sbmilekic NULL); 93248745Swpaul wb_newbuf(sc, cur_rx, m); 93348745Swpaul if (m0 == NULL) { 93448745Swpaul ifp->if_ierrors++; 93550675Swpaul break; 93641502Swpaul } 93748745Swpaul m = m0; 93841502Swpaul 93941502Swpaul ifp->if_ipackets++; 940122689Ssam WB_UNLOCK(sc); 941106936Ssam (*ifp->if_input)(ifp, m); 942122689Ssam WB_LOCK(sc); 94341502Swpaul } 94441502Swpaul} 94541502Swpaul 946105221Sphkstatic void 947102336Salfredwb_rxeoc(sc) 94841502Swpaul struct wb_softc *sc; 94941502Swpaul{ 95041502Swpaul wb_rxeof(sc); 95141502Swpaul 95241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 95341502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 95441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 95541502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 95641502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 95741502Swpaul} 95841502Swpaul 95941502Swpaul/* 96041502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 96141502Swpaul * the list buffers. 96241502Swpaul */ 963102336Salfredstatic void 964102336Salfredwb_txeof(sc) 96541502Swpaul struct wb_softc *sc; 96641502Swpaul{ 96741502Swpaul struct wb_chain *cur_tx; 96841502Swpaul struct ifnet *ifp; 96941502Swpaul 970147256Sbrooks ifp = sc->wb_ifp; 97141502Swpaul 97241502Swpaul /* Clear the timeout timer. */ 973199560Sjhb sc->wb_timer = 0; 97441502Swpaul 97541502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 97641502Swpaul return; 97741502Swpaul 97841502Swpaul /* 97941502Swpaul * Go through our tx list and free mbufs for those 98041502Swpaul * frames that have been transmitted. 98141502Swpaul */ 98241502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 98341502Swpaul u_int32_t txstat; 98441502Swpaul 98541502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 98641502Swpaul txstat = WB_TXSTATUS(cur_tx); 98741502Swpaul 98841502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 98941502Swpaul break; 99041502Swpaul 99141502Swpaul if (txstat & WB_TXSTAT_TXERR) { 99241502Swpaul ifp->if_oerrors++; 99341502Swpaul if (txstat & WB_TXSTAT_ABORT) 99441502Swpaul ifp->if_collisions++; 99541502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 99641502Swpaul ifp->if_collisions++; 99741502Swpaul } 99841502Swpaul 99941502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 100041502Swpaul 100141502Swpaul ifp->if_opackets++; 100241502Swpaul m_freem(cur_tx->wb_mbuf); 100341502Swpaul cur_tx->wb_mbuf = NULL; 100441502Swpaul 100541502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 100641502Swpaul sc->wb_cdata.wb_tx_head = NULL; 100741502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 100841502Swpaul break; 100941502Swpaul } 101041502Swpaul 101141502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 101241502Swpaul } 101341502Swpaul} 101441502Swpaul 101541502Swpaul/* 101641502Swpaul * TX 'end of channel' interrupt handler. 101741502Swpaul */ 1018102336Salfredstatic void 1019102336Salfredwb_txeoc(sc) 102041502Swpaul struct wb_softc *sc; 102141502Swpaul{ 102241502Swpaul struct ifnet *ifp; 102341502Swpaul 1024147256Sbrooks ifp = sc->wb_ifp; 102541502Swpaul 1026199560Sjhb sc->wb_timer = 0; 102741502Swpaul 102841502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 1029148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 103041502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 103141502Swpaul } else { 103241502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 103341502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1034199560Sjhb sc->wb_timer = 5; 103541502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 103641502Swpaul } 103741502Swpaul } 103841502Swpaul} 103941502Swpaul 1040102336Salfredstatic void 1041102336Salfredwb_intr(arg) 104241502Swpaul void *arg; 104341502Swpaul{ 104441502Swpaul struct wb_softc *sc; 104541502Swpaul struct ifnet *ifp; 104641502Swpaul u_int32_t status; 104741502Swpaul 104841502Swpaul sc = arg; 104967087Swpaul WB_LOCK(sc); 1050147256Sbrooks ifp = sc->wb_ifp; 105141502Swpaul 1052151774Sjhb if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 105367087Swpaul WB_UNLOCK(sc); 105441502Swpaul return; 105567087Swpaul } 105641502Swpaul 105741502Swpaul /* Disable interrupts. */ 105841502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 105941502Swpaul 106041502Swpaul for (;;) { 106141502Swpaul 106241502Swpaul status = CSR_READ_4(sc, WB_ISR); 106341502Swpaul if (status) 106441502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 106541502Swpaul 106641502Swpaul if ((status & WB_INTRS) == 0) 106741502Swpaul break; 106841502Swpaul 106941502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 107041502Swpaul ifp->if_ierrors++; 107141502Swpaul wb_reset(sc); 107250675Swpaul if (status & WB_ISR_RX_ERR) 107350675Swpaul wb_fixmedia(sc); 1074151774Sjhb wb_init_locked(sc); 107550675Swpaul continue; 107641502Swpaul } 107741502Swpaul 107850675Swpaul if (status & WB_ISR_RX_OK) 107950675Swpaul wb_rxeof(sc); 108050675Swpaul 108150675Swpaul if (status & WB_ISR_RX_IDLE) 108250675Swpaul wb_rxeoc(sc); 108350675Swpaul 108441502Swpaul if (status & WB_ISR_TX_OK) 108541502Swpaul wb_txeof(sc); 108641502Swpaul 108741502Swpaul if (status & WB_ISR_TX_NOBUF) 108841502Swpaul wb_txeoc(sc); 108941502Swpaul 109041502Swpaul if (status & WB_ISR_TX_IDLE) { 109141502Swpaul wb_txeof(sc); 109241502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 109341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 109441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 109541502Swpaul } 109641502Swpaul } 109741502Swpaul 109841502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 109941502Swpaul ifp->if_oerrors++; 110041502Swpaul wb_txeof(sc); 110141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 110241502Swpaul /* Jack up TX threshold */ 110341502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 110441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 110541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 110641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 110741502Swpaul } 110841502Swpaul 110941502Swpaul if (status & WB_ISR_BUS_ERR) { 111041502Swpaul wb_reset(sc); 1111151774Sjhb wb_init_locked(sc); 111241502Swpaul } 111341502Swpaul 111441502Swpaul } 111541502Swpaul 111641502Swpaul /* Re-enable interrupts. */ 111741502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 111841502Swpaul 111941502Swpaul if (ifp->if_snd.ifq_head != NULL) { 1120151774Sjhb wb_start_locked(ifp); 112141502Swpaul } 112241502Swpaul 112367087Swpaul WB_UNLOCK(sc); 112441502Swpaul} 112541502Swpaul 1126102336Salfredstatic void 1127102336Salfredwb_tick(xsc) 112850675Swpaul void *xsc; 112950675Swpaul{ 113050675Swpaul struct wb_softc *sc; 113150675Swpaul struct mii_data *mii; 113250675Swpaul 113350675Swpaul sc = xsc; 1134151774Sjhb WB_LOCK_ASSERT(sc); 113550675Swpaul mii = device_get_softc(sc->wb_miibus); 113650675Swpaul 113750675Swpaul mii_tick(mii); 113850675Swpaul 1139199560Sjhb if (sc->wb_timer > 0 && --sc->wb_timer == 0) 1140199560Sjhb wb_watchdog(sc); 1141151774Sjhb callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 114250675Swpaul} 114350675Swpaul 114441502Swpaul/* 114541502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 114641502Swpaul * pointers to the fragment pointers. 114741502Swpaul */ 1148102336Salfredstatic int 1149102336Salfredwb_encap(sc, c, m_head) 115041502Swpaul struct wb_softc *sc; 115141502Swpaul struct wb_chain *c; 115241502Swpaul struct mbuf *m_head; 115341502Swpaul{ 115441502Swpaul int frag = 0; 115541502Swpaul struct wb_desc *f = NULL; 115641502Swpaul int total_len; 115741502Swpaul struct mbuf *m; 115841502Swpaul 115941502Swpaul /* 116041502Swpaul * Start packing the mbufs in this chain into 116141502Swpaul * the fragment pointers. Stop when we run out 116241502Swpaul * of fragments or hit the end of the mbuf chain. 116341502Swpaul */ 116441502Swpaul m = m_head; 116541502Swpaul total_len = 0; 116641502Swpaul 116741502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 116841502Swpaul if (m->m_len != 0) { 116941502Swpaul if (frag == WB_MAXFRAGS) 117041502Swpaul break; 117141502Swpaul total_len += m->m_len; 117241502Swpaul f = &c->wb_ptr->wb_frag[frag]; 117341502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 117441502Swpaul if (frag == 0) { 117541502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 117641502Swpaul f->wb_status = 0; 117741502Swpaul } else 117841502Swpaul f->wb_status = WB_TXSTAT_OWN; 117941502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 118041502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 118141502Swpaul frag++; 118241502Swpaul } 118341502Swpaul } 118441502Swpaul 118541502Swpaul /* 118641502Swpaul * Handle special case: we used up all 16 fragments, 118741502Swpaul * but we have more mbufs left in the chain. Copy the 118841502Swpaul * data into an mbuf cluster. Note that we don't 118941502Swpaul * bother clearing the values in the other fragment 119041502Swpaul * pointers/counters; it wouldn't gain us anything, 119141502Swpaul * and would waste cycles. 119241502Swpaul */ 119341502Swpaul if (m != NULL) { 119441502Swpaul struct mbuf *m_new = NULL; 119541502Swpaul 1196248078Smarius MGETHDR(m_new, M_NOWAIT, MT_DATA); 119787846Sluigi if (m_new == NULL) 119841502Swpaul return(1); 119941502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1200248078Smarius MCLGET(m_new, M_NOWAIT); 120141502Swpaul if (!(m_new->m_flags & M_EXT)) { 120241502Swpaul m_freem(m_new); 120341502Swpaul return(1); 120441502Swpaul } 120541502Swpaul } 120641502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 120741502Swpaul mtod(m_new, caddr_t)); 120841502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 120941502Swpaul m_freem(m_head); 121041502Swpaul m_head = m_new; 121141502Swpaul f = &c->wb_ptr->wb_frag[0]; 121241502Swpaul f->wb_status = 0; 121341502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 121441502Swpaul f->wb_ctl = total_len = m_new->m_len; 121541502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 121641502Swpaul frag = 1; 121741502Swpaul } 121841502Swpaul 121941502Swpaul if (total_len < WB_MIN_FRAMELEN) { 122041502Swpaul f = &c->wb_ptr->wb_frag[frag]; 122141502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 122241502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 122341502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 122441502Swpaul f->wb_status = WB_TXSTAT_OWN; 122541502Swpaul frag++; 122641502Swpaul } 122741502Swpaul 122841502Swpaul c->wb_mbuf = m_head; 122941502Swpaul c->wb_lastdesc = frag - 1; 123041502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 123141502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 123241502Swpaul 123341502Swpaul return(0); 123441502Swpaul} 123541502Swpaul 123641502Swpaul/* 123741502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 123841502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 123941502Swpaul * copy of the pointers since the transmit list fragment pointers are 124041502Swpaul * physical addresses. 124141502Swpaul */ 124241502Swpaul 1243102336Salfredstatic void 1244102336Salfredwb_start(ifp) 124541502Swpaul struct ifnet *ifp; 124641502Swpaul{ 124741502Swpaul struct wb_softc *sc; 1248151774Sjhb 1249151774Sjhb sc = ifp->if_softc; 1250151774Sjhb WB_LOCK(sc); 1251151774Sjhb wb_start_locked(ifp); 1252151774Sjhb WB_UNLOCK(sc); 1253151774Sjhb} 1254151774Sjhb 1255151774Sjhbstatic void 1256151774Sjhbwb_start_locked(ifp) 1257151774Sjhb struct ifnet *ifp; 1258151774Sjhb{ 1259151774Sjhb struct wb_softc *sc; 126041502Swpaul struct mbuf *m_head = NULL; 126141502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 126241502Swpaul 126341502Swpaul sc = ifp->if_softc; 1264151774Sjhb WB_LOCK_ASSERT(sc); 126541502Swpaul 126641502Swpaul /* 126741502Swpaul * Check for an available queue slot. If there are none, 126841502Swpaul * punt. 126941502Swpaul */ 127041502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1271148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 127241502Swpaul return; 127341502Swpaul } 127441502Swpaul 127541502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 127641502Swpaul 127741502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 127841502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 127941502Swpaul if (m_head == NULL) 128041502Swpaul break; 128141502Swpaul 128241502Swpaul /* Pick a descriptor off the free list. */ 128341502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 128441502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 128541502Swpaul 128641502Swpaul /* Pack the data into the descriptor. */ 128741502Swpaul wb_encap(sc, cur_tx, m_head); 128841502Swpaul 128941502Swpaul if (cur_tx != start_tx) 129041502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 129141502Swpaul 129241502Swpaul /* 129341502Swpaul * If there's a BPF listener, bounce a copy of this frame 129441502Swpaul * to him. 129541502Swpaul */ 1296106936Ssam BPF_MTAP(ifp, cur_tx->wb_mbuf); 129741502Swpaul } 129841502Swpaul 129941502Swpaul /* 130041526Swpaul * If there are no packets queued, bail. 130141526Swpaul */ 1302151774Sjhb if (cur_tx == NULL) 130341526Swpaul return; 130441526Swpaul 130541526Swpaul /* 130641502Swpaul * Place the request for the upload interrupt 130741502Swpaul * in the last descriptor in the chain. This way, if 130841502Swpaul * we're chaining several packets at once, we'll only 1309172568Skevlo * get an interrupt once for the whole chain rather than 131041502Swpaul * once for each packet. 131141502Swpaul */ 131241502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 131342718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 131441502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 131541502Swpaul 131641502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 131741502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 131841502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 131941502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 132041502Swpaul } else { 132141502Swpaul /* 132241502Swpaul * We need to distinguish between the case where 132341502Swpaul * the own bit is clear because the chip cleared it 132441502Swpaul * and where the own bit is clear because we haven't 132541502Swpaul * set it yet. The magic value WB_UNSET is just some 132641502Swpaul * ramdomly chosen number which doesn't have the own 132741502Swpaul * bit set. When we actually transmit the frame, the 132841502Swpaul * status word will have _only_ the own bit set, so 132941502Swpaul * the txeoc handler will be able to tell if it needs 133041502Swpaul * to initiate another transmission to flush out pending 133141502Swpaul * frames. 133241502Swpaul */ 133341502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 133441502Swpaul } 133541502Swpaul 133641502Swpaul /* 133741502Swpaul * Set a timeout in case the chip goes out to lunch. 133841502Swpaul */ 1339199560Sjhb sc->wb_timer = 5; 134041502Swpaul} 134141502Swpaul 1342102336Salfredstatic void 1343102336Salfredwb_init(xsc) 134441502Swpaul void *xsc; 134541502Swpaul{ 134641502Swpaul struct wb_softc *sc = xsc; 1347151774Sjhb 1348151774Sjhb WB_LOCK(sc); 1349151774Sjhb wb_init_locked(sc); 1350151774Sjhb WB_UNLOCK(sc); 1351151774Sjhb} 1352151774Sjhb 1353151774Sjhbstatic void 1354151774Sjhbwb_init_locked(sc) 1355151774Sjhb struct wb_softc *sc; 1356151774Sjhb{ 1357147256Sbrooks struct ifnet *ifp = sc->wb_ifp; 135867087Swpaul int i; 135950675Swpaul struct mii_data *mii; 136041502Swpaul 1361151774Sjhb WB_LOCK_ASSERT(sc); 136250675Swpaul mii = device_get_softc(sc->wb_miibus); 136341502Swpaul 136441502Swpaul /* 136541502Swpaul * Cancel pending I/O and free all RX/TX buffers. 136641502Swpaul */ 136741502Swpaul wb_stop(sc); 136841502Swpaul wb_reset(sc); 136941502Swpaul 137041502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 137141502Swpaul 137241502Swpaul /* 137341502Swpaul * Set cache alignment and burst length. 137441502Swpaul */ 137550675Swpaul#ifdef foo 137641502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 137741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 137841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 137950675Swpaul#endif 138041502Swpaul 138150675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 138250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 138350675Swpaul switch(sc->wb_cachesize) { 138450675Swpaul case 32: 138550675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 138650675Swpaul break; 138750675Swpaul case 16: 138850675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 138950675Swpaul break; 139050675Swpaul case 8: 139150675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 139250675Swpaul break; 139350675Swpaul case 0: 139450675Swpaul default: 139550675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 139650675Swpaul break; 139750675Swpaul } 139850675Swpaul 139941502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 140041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 140141502Swpaul 140241502Swpaul /* Init our MAC address */ 140341502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 1404152315Sru CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]); 140541502Swpaul } 140641502Swpaul 140741502Swpaul /* Init circular RX list. */ 140841502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 1409162315Sglebius device_printf(sc->wb_dev, 1410149677Sjhb "initialization failed: no memory for rx buffers\n"); 141141502Swpaul wb_stop(sc); 141241502Swpaul return; 141341502Swpaul } 141441502Swpaul 141541502Swpaul /* Init TX descriptors. */ 141641502Swpaul wb_list_tx_init(sc); 141741502Swpaul 141841502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 141941502Swpaul if (ifp->if_flags & IFF_PROMISC) { 142041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 142141502Swpaul } else { 142241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 142341502Swpaul } 142441502Swpaul 142541502Swpaul /* 142641502Swpaul * Set capture broadcast bit to capture broadcast frames. 142741502Swpaul */ 142841502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 142941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 143041502Swpaul } else { 143141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 143241502Swpaul } 143341502Swpaul 143441502Swpaul /* 143541502Swpaul * Program the multicast filter, if necessary. 143641502Swpaul */ 143741502Swpaul wb_setmulti(sc); 143841502Swpaul 143941502Swpaul /* 144041502Swpaul * Load the address of the RX list. 144141502Swpaul */ 144241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 144341502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 144441502Swpaul 144541502Swpaul /* 144641502Swpaul * Enable interrupts. 144741502Swpaul */ 144841502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 144941502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 145041502Swpaul 145141502Swpaul /* Enable receiver and transmitter. */ 145241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 145341502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 145441502Swpaul 145541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 145641502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 145741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 145841502Swpaul 145950675Swpaul mii_mediachg(mii); 146041502Swpaul 1461148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 1462148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 146341502Swpaul 1464151774Sjhb callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 146541502Swpaul} 146641502Swpaul 146741502Swpaul/* 146841502Swpaul * Set media options. 146941502Swpaul */ 1470102336Salfredstatic int 1471102336Salfredwb_ifmedia_upd(ifp) 147241502Swpaul struct ifnet *ifp; 147341502Swpaul{ 147441502Swpaul struct wb_softc *sc; 147541502Swpaul 147641502Swpaul sc = ifp->if_softc; 147741502Swpaul 1478151774Sjhb WB_LOCK(sc); 147950675Swpaul if (ifp->if_flags & IFF_UP) 1480151774Sjhb wb_init_locked(sc); 1481151774Sjhb WB_UNLOCK(sc); 148241502Swpaul 148341502Swpaul return(0); 148441502Swpaul} 148541502Swpaul 148641502Swpaul/* 148741502Swpaul * Report current media status. 148841502Swpaul */ 1489102336Salfredstatic void 1490102336Salfredwb_ifmedia_sts(ifp, ifmr) 149141502Swpaul struct ifnet *ifp; 149241502Swpaul struct ifmediareq *ifmr; 149341502Swpaul{ 149441502Swpaul struct wb_softc *sc; 149550675Swpaul struct mii_data *mii; 149641502Swpaul 149741502Swpaul sc = ifp->if_softc; 149841502Swpaul 1499151774Sjhb WB_LOCK(sc); 150050675Swpaul mii = device_get_softc(sc->wb_miibus); 150141502Swpaul 150250675Swpaul mii_pollstat(mii); 150350675Swpaul ifmr->ifm_active = mii->mii_media_active; 150450675Swpaul ifmr->ifm_status = mii->mii_media_status; 1505151774Sjhb WB_UNLOCK(sc); 150641502Swpaul} 150741502Swpaul 1508102336Salfredstatic int 1509102336Salfredwb_ioctl(ifp, command, data) 151041502Swpaul struct ifnet *ifp; 151141502Swpaul u_long command; 151241502Swpaul caddr_t data; 151341502Swpaul{ 151441502Swpaul struct wb_softc *sc = ifp->if_softc; 151550675Swpaul struct mii_data *mii; 151641502Swpaul struct ifreq *ifr = (struct ifreq *) data; 151767087Swpaul int error = 0; 151841502Swpaul 151941502Swpaul switch(command) { 152041502Swpaul case SIOCSIFFLAGS: 1521151774Sjhb WB_LOCK(sc); 152241502Swpaul if (ifp->if_flags & IFF_UP) { 1523151774Sjhb wb_init_locked(sc); 152441502Swpaul } else { 1525148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 152641502Swpaul wb_stop(sc); 152741502Swpaul } 1528151774Sjhb WB_UNLOCK(sc); 152941502Swpaul error = 0; 153041502Swpaul break; 153141502Swpaul case SIOCADDMULTI: 153241502Swpaul case SIOCDELMULTI: 1533151774Sjhb WB_LOCK(sc); 153441502Swpaul wb_setmulti(sc); 1535151774Sjhb WB_UNLOCK(sc); 153641502Swpaul error = 0; 153741502Swpaul break; 153841502Swpaul case SIOCGIFMEDIA: 153941502Swpaul case SIOCSIFMEDIA: 154050675Swpaul mii = device_get_softc(sc->wb_miibus); 154150675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 154241502Swpaul break; 154341502Swpaul default: 1544106936Ssam error = ether_ioctl(ifp, command, data); 154541502Swpaul break; 154641502Swpaul } 154741502Swpaul 154841502Swpaul return(error); 154941502Swpaul} 155041502Swpaul 1551102336Salfredstatic void 1552199560Sjhbwb_watchdog(sc) 1553199560Sjhb struct wb_softc *sc; 1554199560Sjhb{ 155541502Swpaul struct ifnet *ifp; 155641502Swpaul 1557199560Sjhb WB_LOCK_ASSERT(sc); 1558199560Sjhb ifp = sc->wb_ifp; 155941502Swpaul ifp->if_oerrors++; 1560149677Sjhb if_printf(ifp, "watchdog timeout\n"); 156150675Swpaul#ifdef foo 156241502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1563149677Sjhb if_printf(ifp, "no carrier - transceiver cable problem?\n"); 156450675Swpaul#endif 156541502Swpaul wb_stop(sc); 156641502Swpaul wb_reset(sc); 1567151774Sjhb wb_init_locked(sc); 156841502Swpaul 156941502Swpaul if (ifp->if_snd.ifq_head != NULL) 1570151774Sjhb wb_start_locked(ifp); 157141502Swpaul} 157241502Swpaul 157341502Swpaul/* 157441502Swpaul * Stop the adapter and free any mbufs allocated to the 157541502Swpaul * RX and TX lists. 157641502Swpaul */ 1577102336Salfredstatic void 1578102336Salfredwb_stop(sc) 157941502Swpaul struct wb_softc *sc; 158041502Swpaul{ 158141502Swpaul register int i; 158241502Swpaul struct ifnet *ifp; 158341502Swpaul 1584151774Sjhb WB_LOCK_ASSERT(sc); 1585147256Sbrooks ifp = sc->wb_ifp; 1586199560Sjhb sc->wb_timer = 0; 158741502Swpaul 1588151774Sjhb callout_stop(&sc->wb_stat_callout); 158950675Swpaul 159041502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 159141502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 159241502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 159341502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 159441502Swpaul 159541502Swpaul /* 159641502Swpaul * Free data in the RX lists. 159741502Swpaul */ 159841502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 159941502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 160041502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 160141502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 160241502Swpaul } 160341502Swpaul } 160441502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 160541502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 160641502Swpaul 160741502Swpaul /* 160841502Swpaul * Free the TX list buffers. 160941502Swpaul */ 161041502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 161141502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 161241502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 161341502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 161441502Swpaul } 161541502Swpaul } 161641502Swpaul 161741502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 161841502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 161941502Swpaul 1620148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 162141502Swpaul} 162241502Swpaul 162341502Swpaul/* 162441502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 162541502Swpaul * get confused by errant DMAs when rebooting. 162641502Swpaul */ 1627194023Savgstatic int 1628102336Salfredwb_shutdown(dev) 162949611Swpaul device_t dev; 163041502Swpaul{ 163149611Swpaul struct wb_softc *sc; 163241502Swpaul 163349611Swpaul sc = device_get_softc(dev); 1634151774Sjhb 1635151774Sjhb WB_LOCK(sc); 163641502Swpaul wb_stop(sc); 1637151774Sjhb WB_UNLOCK(sc); 163841502Swpaul 1639194023Savg return (0); 164041502Swpaul} 1641