Searched refs:v8i8 (Results 1 - 19 of 19) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp215 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0},
216 {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 0},
252 {ISD::TRUNCATE, MVT::v8i16, MVT::v8i8, 0},
282 { ISD::ADD, MVT::v8i16, MVT::v8i8, 0 },
285 { ISD::SUB, MVT::v8i16, MVT::v8i8, 0 },
288 { ISD::MUL, MVT::v8i16, MVT::v8i8, 0 },
291 { ISD::SHL, MVT::v8i16, MVT::v8i8, 0 },
332 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
333 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
342 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8,
[all...]
H A DARMISelDAGToDAG.cpp1781 } else if (LoadedVT == MVT::v8i8 &&
2079 case MVT::v8i8: OpcodeIndex = 0; break;
2224 case MVT::v8i8: OpcodeIndex = 0; break;
2394 case MVT::v8i8: OpcodeIndex = 0; break;
2926 case MVT::v8i8:
3923 case MVT::v8i8: Opc = ARM::VZIPd8; break;
3946 case MVT::v8i8: Opc = ARM::VUZPd8; break;
3969 case MVT::v8i8: Opc = ARM::VTRNd8; break;
H A DARMISelLowering.cpp401 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
405 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
415 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
420 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
787 addDRTypeForNEON(MVT::v8i8);
890 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
892 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
911 // v8i8/v16i8 vcnt instruction.
923 setOperationAction(ISD::CTTZ, MVT::v8i8, Custo
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1014 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw
1025 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw
1031 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw
1394 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, member in class:MVT
1407 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, member in class:MVT
1421 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm member in class:MVT
1454 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd
1469 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 },
1484 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 },
1485 { ISD::ZERO_EXTEND, MVT::v8i8, MV
1569 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, member in class:MVT
1580 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, member in class:MVT
1591 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb member in class:MVT
[all...]
H A DX86ISelLowering.cpp877 for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
887 setOperationAction(ISD::MUL, MVT::v8i8, Custom);
973 for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) {
1007 setOperationAction(ISD::LOAD, MVT::v8i8, Custom);
1010 setOperationAction(ISD::STORE, MVT::v8i8, Custom);
1014 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1029 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
1113 setLoadExtAction(LoadExtOp, MVT::v8i16, MVT::v8i8, Legal);
1328 setLoadExtAction(LoadExtOp, MVT::v8i32, MVT::v8i8, Legal);
1469 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Lega
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp315 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
323 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
324 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
327 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
328 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
359 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
361 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
1018 {ISD::ADD, MVT::v8i8, 1}, member in class:MVT
1038 { TTI::SK_Broadcast, MVT::v8i8, 1 },
1050 { TTI::SK_Transpose, MVT::v8i8,
[all...]
H A DAArch64ISelDAGToDAG.cpp3505 if (VT == MVT::v8i8) {
3532 if (VT == MVT::v8i8) {
3559 if (VT == MVT::v8i8) {
3586 if (VT == MVT::v8i8) {
3613 if (VT == MVT::v8i8) {
3640 if (VT == MVT::v8i8) {
3667 if (VT == MVT::v8i8) {
3694 if (VT == MVT::v8i8) {
3721 if (VT == MVT::v8i8) {
3748 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
[all...]
H A DAArch64ISelLowering.cpp158 addDRTypeForNEON(MVT::v8i8);
802 // i8 vector elements also need promotion to i32 for v8i8
803 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32);
804 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i8, MVT::v8i32);
839 for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
969 for (auto VT : {MVT::v8i8, MVT::v4i16})
1027 if (VT != MVT::v8i8 && VT != MVT::v16i8)
1292 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
3327 // It first extend the promoted v4i16 to v8i16, truncate to v8i8, and extract
3340 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::v8i8, TruncEx
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h76 v8i8 = 29, // 8 x i8
364 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 ||
478 case v8i8:
660 case v8i8:
817 case v8i8:
1034 if (NumElements == 8) return MVT::v8i8;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp619 VT == MVT::v4i16 || VT == MVT::v8i8 ||
1454 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1666 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1686 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
1692 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
1710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1737 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
H A DHexagonISelDAGToDAG.cpp105 case MVT::v8i8:
495 case MVT::v8i8:
H A DHexagonISelLoweringHVX.cpp908 // Combine the two low words from ShuffV into a v8i8, and byte-compare
913 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0});
H A DHexagonInstrInfo.cpp2684 case MVT::v8i8:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp225 case MVT::v8i8:
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp94 case MVT::v8i8: return "MVT::v8i8";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp246 setLoadExtAction(Ext, MVT::v8i16, MVT::v8i8, Legal);
606 return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) ||
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp215 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Expand);
220 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
225 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Expand);
399 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom);
403 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
765 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
H A DR600ISelLowering.cpp117 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Custom);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp757 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);

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