Lines Matching refs:v8i8
158 addDRTypeForNEON(MVT::v8i8);
802 // i8 vector elements also need promotion to i32 for v8i8
803 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32);
804 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i8, MVT::v8i32);
839 for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
969 for (auto VT : {MVT::v8i8, MVT::v4i16})
1027 if (VT != MVT::v8i8 && VT != MVT::v16i8)
1292 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
3327 // It first extend the promoted v4i16 to v8i16, truncate to v8i8, and extract
3340 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::v8i8, TruncExt);
5593 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
5595 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
5618 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5622 // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds.
7588 MVT IndexVT = MVT::v8i8;
8100 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
8642 // the upper bits of the lowest lane (e.g. v8i8, v4i16).
8683 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
8718 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
11176 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
11206 // (v16i8 (concat_vectors (v8i8 (urhadd (extract_subvector (v16i8 OpA, <0>),
11209 // (v8i8 (urhadd (extract_subvector (v16i8 OpA, <8>),
12123 // %result = v8i32 sext v8i8 %value
12135 // This implies that the most efficient way to do the extend from v8i8
12136 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
14574 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,