Lines Matching refs:v8i8
401 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
405 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
415 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
420 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
787 addDRTypeForNEON(MVT::v8i8);
890 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
892 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
911 // v8i8/v16i8 vcnt instruction.
923 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
933 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
958 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
1570 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
5785 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
6205 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
6209 // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds.
6641 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
6977 return VT == MVT::v8i8 && M.size() == 8;
8046 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
8047 DAG.getBuildVector(MVT::v8i8, DL, VTBLMask));
8049 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
8050 DAG.getBuildVector(MVT::v8i8, DL, VTBLMask));
8434 if (ST->hasNEON() && VT == MVT::v8i8)
9021 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
9029 if (VT == MVT::v8i8) {
9048 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
9058 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
9066 if (VT == MVT::v8i8) {
9085 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
15349 ExtVT = MVT::v8i8;
16149 if ((Ty == MVT::v4i8 || Ty == MVT::v8i8 || Ty == MVT::v4i16) &&
16867 } else if (VT == MVT::v4i8 || VT == MVT::v8i8) {