| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 55 /// setRegClass - Set the register class of the specified virtual register.
58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { function in class:MachineRegisterInfo
80 MRI.setRegClass(Reg, NewRC);
142 setRegClass(Reg, NewRC);
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| H A D | TailDuplicator.cpp | 422 MRI->setRegClass(VI->second.Reg, ConstrRC);
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| H A D | MachineLICM.cpp | 1454 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
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| H A D | RegisterCoalescer.cpp | 1396 MRI->setRegClass(DstReg, NewRC);
1967 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
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| H A D | ModuloSchedule.cpp | 1904 MRI.setRegClass(R, MRI.getRegClass(PhiR));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 223 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
275 MRI.setRegClass(DstReg, DstRC);
813 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0));
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| H A D | SILowerI1Copies.cpp | 576 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
697 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
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| H A D | AMDGPUInstructionSelector.cpp | 163 MRI->setRegClass(SrcReg, SrcRC);
312 MRI->setRegClass(Src0.getReg(), RC);
314 MRI->setRegClass(Src1.getReg(), RC);
478 MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass);
878 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
1087 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
1645 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI));
2253 MRI->setRegClass(
2293 MRI->setRegClass(CondReg, ConstrainRC);
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| H A D | AMDGPURegisterBankInfo.cpp | 919 MRI.setRegClass(UnmergePiece, &AMDGPU::VReg_64RegClass);
920 MRI.setRegClass(CurrentLaneOpRegLo, &AMDGPU::SReg_32_XM0RegClass);
921 MRI.setRegClass(CurrentLaneOpRegHi, &AMDGPU::SReg_32_XM0RegClass);
938 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_64_XEXECRegClass);
951 MRI.setRegClass(UnmergePiece, &AMDGPU::VGPR_32RegClass);
952 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_32_XM0RegClass);
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| H A D | AMDGPULegalizerInfo.cpp | 2062 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass);
4192 MRI.setRegClass(Def, TRI->getWaveMaskRegClass());
4193 MRI.setRegClass(Use, TRI->getWaveMaskRegClass());
4223 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass());
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| H A D | SIISelLowering.cpp | 10977 MRI.setRegClass(Op.getReg(), NewRC);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 417 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
1318 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1322 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1335 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1344 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
2419 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2421 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
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| H A D | PPCMIPeephole.cpp | 803 MRI->setRegClass(DominatorReg, TRC);
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| H A D | PPCInstrInfo.cpp | 4230 MRI.setRegClass(RegToModify, NewRC);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 1306 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
1308 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass);
1310 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass);
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 669 /// setRegClass - Set the register class of the specified virtual register.
670 void setRegClass(Register Reg, const TargetRegisterClass *RC);
749 /// undefined on an incomplete register until one of setRegClass(),
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 612 MRI.setRegClass(Reg, Info.D.RC);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBankInfo.cpp | 146 MRI.setRegClass(Reg, &RC);
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| H A D | IRTranslator.cpp | 1189 MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 687 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86DomainReassignment.cpp | 511 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 655 MRI->setRegClass(NewVReg, SRC);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 580 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 3382 MRI->setRegClass(UseMI.getOperand(0).getReg(), TRC);
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