Searched refs:SrcVT (Results 1 - 25 of 36) sorted by relevance

12

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp173 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
830 MVT SrcVT = SrcEVT.getSimpleVT();
832 if (SrcVT == MVT::i1 && Subtarget->useCRBits())
846 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
847 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
872 switch (SrcVT.SimpleTy) {
937 if (!PPCEmitIntExt(SrcVT, SrcReg
962 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
980 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
1021 PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg, bool IsSigned) argument
1192 MVT DstVT, SrcVT; local
1804 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1875 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
998 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
1001 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1077 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
1080 if (SrcVT !
1211 MVT SrcVT = ArgVT; local
1219 MVT SrcVT = ArgVT; local
1783 EVT SrcVT, DestVT; local
1830 emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1849 emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1864 emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1873 emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1895 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1909 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp961 EVT SrcVT = Src.getValueType(); local
962 int NumSrcElements = SrcVT.getVectorNumElements();
964 // *_EXTEND_VECTOR_INREG SrcVT can be smaller than VT - so insert the vector
966 if (SrcVT.bitsLE(VT)) {
967 assert((VT.getSizeInBits() % SrcVT.getScalarSizeInBits()) == 0 &&
969 NumSrcElements = VT.getSizeInBits() / SrcVT.getScalarSizeInBits();
970 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(),
972 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT),
995 EVT SrcVT = Src.getValueType(); local
1020 EVT SrcVT = Src.getValueType(); local
[all...]
H A DTargetLowering.cpp645 EVT SrcVT = Src.getValueType(); local
647 if (SrcVT == DstVT)
650 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits();
658 if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0 &&
661 unsigned NumSrcElts = SrcVT.getVectorNumElements();
684 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
794 EVT SrcVT = Src.getValueType(); local
796 if (DemandedElts == 1 && DstVT.getSizeInBits() == SrcVT.getSizeInBits() &&
798 DemandedBits.getActiveBits() <= SrcVT
1833 EVT SrcVT = Src.getValueType(); local
1866 EVT SrcVT = Src.getValueType(); local
1914 EVT SrcVT = Src.getValueType(); local
2052 EVT SrcVT = Src.getValueType(); local
2375 EVT SrcVT = Src.getValueType(); local
[all...]
H A DLegalizeDAG.cpp720 EVT SrcVT = LD->getMemoryVT();
721 unsigned SrcWidth = SrcVT.getSizeInBits();
725 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
733 (SrcVT != MVT::i1 ||
738 unsigned NewWidth = SrcVT.getStoreSizeInBits();
743 // way. A zext load from NVT thus automatically gives zext from SrcVT.
758 Result, DAG.getValueType(SrcVT));
763 DAG.getValueType(SrcVT));
769 assert(!SrcVT.isVector() && "Unsupported extload!");
845 SrcVT
[all...]
H A DFastISel.cpp1524 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local
1527 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1537 if (!TLI.isTypeLegal(SrcVT))
1547 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1574 MVT SrcVT = SrcEVT.getSimpleVT();
1583 if (SrcVT == DstVT) {
1584 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1596 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1951 EVT SrcVT local
[all...]
H A DLegalizeFloatTypes.cpp1602 EVT SrcVT = Src.getValueType(); local
1609 if (SrcVT.bitsLE(MVT::i32)) {
1618 if (SrcVT.bitsLE(MVT::i64)) {
1622 } else if (SrcVT.bitsLE(MVT::i128)) {
1639 SrcVT = Src.getValueType();
1647 switch (SrcVT.getSimpleVT().SimpleTy) {
1666 Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT),
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
233 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
264 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
268 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
272 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1181 MVT SrcVT = RetVT; local
1208 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1306 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
2879 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
2880 if (SrcVT
2919 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); local
3091 MVT SrcVT = ArgVT; local
3101 MVT SrcVT = ArgVT; local
4111 emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4218 emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4339 emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4421 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool IsZExt) argument
4530 optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT) argument
4588 MVT SrcVT; local
4702 MVT SrcVT = VT; local
4768 MVT SrcVT = RetVT; local
4847 MVT RetVT, SrcVT; local
[all...]
H A DAArch64TargetTransformInfo.cpp438 auto SrcVT = TLI->getValueType(DL, Src); local
449 if (DstVT.getSizeInBits() < SrcVT.getSizeInBits())
464 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u)
H A DAArch64ISelLowering.cpp2721 EVT SrcVT = SrcVal.getValueType(); local
2723 if (SrcVT != MVT::f128) {
2725 if (useSVEForFixedLengthVectorVT(SrcVT))
2733 LC = RTLIB::getFPROUND(SrcVT, Op.getValueType());
5503 EVT SrcVT = In2.getValueType(); local
5505 if (SrcVT.bitsLT(VT))
5507 else if (SrcVT.bitsGT(VT))
7057 EVT SrcVT = Src.ShuffleVec.getValueType(); local
7059 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
7064 EVT EltVT = SrcVT
9016 EVT SrcVT = LHS.getValueType(); local
10377 isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const argument
12155 EVT SrcVT = Src->getValueType(0); local
13347 EVT SrcVT = N0.getOperand(0).getValueType(); local
13502 const EVT SrcVT = Src->getValueType(0); local
[all...]
H A DAArch64ISelDAGToDAG.cpp544 EVT SrcVT; local
546 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
548 SrcVT = N.getOperand(0).getValueType();
550 if (!IsLoadStore && SrcVT == MVT::i8)
552 else if (!IsLoadStore && SrcVT == MVT::i16)
554 else if (SrcVT == MVT::i32)
556 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
561 EVT SrcVT = N.getOperand(0).getValueType(); local
562 if (!IsLoadStore && SrcVT == MVT::i8)
564 else if (!IsLoadStore && SrcVT
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp204 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1342 MVT SrcVT = SrcEVT.getSimpleVT();
1358 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1359 SrcVT == MVT::i1) {
1373 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1381 switch (SrcVT.SimpleTy) {
1423 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg
2580 EVT SrcVT, DestVT; local
2598 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
[all...]
H A DARMISelLowering.h393 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
561 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DARMISelLowering.cpp5753 EVT SrcVT = Tmp1.getValueType(); local
5770 if (SrcVT == MVT::f32) {
5804 if (SrcVT == MVT::f64)
5967 EVT SrcVT = Op.getValueType(); local
5970 if ((SrcVT == MVT::i16 || SrcVT == MVT::i32) &&
5976 (SrcVT == MVT::f16 || SrcVT == MVT::bf16))
5979 MoveFromHPR(SDLoc(N), DAG, MVT::i32, SrcVT.getSimpleVT(), Op));
5981 if (!(SrcVT
7769 EVT SrcVT = Src.ShuffleVec.getValueType(); local
15895 EVT SrcVT = Src.getValueType(); local
15907 EVT SrcVT = Src.getValueType(); local
16213 isTruncateFree(EVT SrcVT, EVT DstVT) const argument
17829 MVT SrcVT = (Sz == 16 ? MVT::f16 : MVT::f32); local
17855 EVT SrcVT = SrcVal.getValueType(); local
18131 isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp280 EVT SrcVT = Src.getValueType(); local
284 DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)),
H A DX86FastISel.cpp96 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
702 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
705 unsigned Src, EVT SrcVT,
707 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1219 EVT SrcVT = TLI.getValueType(DL, RV->getType()); local
1222 if (SrcVT != DstVT) {
1223 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
1231 if (SrcVT
704 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
2523 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local
3639 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local
[all...]
H A DX86ISelLowering.cpp5190 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
5198 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) &&
6599 EVT SrcVT = Op.getOperand(0).getValueType();
6600 unsigned NumSrcElts = SrcVT.getVectorNumElements();
7569 EVT SrcVT = SrcVec.getValueType();
7570 if (!SrcVT.getScalarType().isByteSized())
7573 unsigned SrcByte = SrcIdx * (SrcVT.getScalarSizeInBits() / 8);
7576 std::min<unsigned>(MinBitsPerElt, SrcVT.getScalarSizeInBits());
7636 EVT SrcVT = Src.getValueType();
7638 if (!SrcVT
[all...]
H A DX86ISelLowering.h1272 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1346 std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
H A DX86ISelDAGToDAG.cpp1142 MVT SrcVT = N->getOperand(0).getSimpleValueType(); local
1146 if (SrcVT.isVector() || DstVT.isVector())
1153 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
1170 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT;
1198 MVT SrcVT = N->getOperand(1).getSimpleValueType(); local
1202 if (SrcVT.isVector() || DstVT.isVector())
1209 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
1226 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT;
1249 assert(SrcVT == MemVT && "Unexpected VT!");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h74 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
76 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
H A DRISCVISelLowering.cpp343 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { argument
344 if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() ||
345 !SrcVT.isInteger() || !DstVT.isInteger())
347 unsigned SrcBits = SrcVT.getSizeInBits();
366 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { argument
367 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTypePromotion.cpp976 EVT SrcVT = TLI->getValueType(DL, I->getType()); local
977 if (SrcVT.isSimple() && TLI->isTypeLegal(SrcVT.getSimpleVT()))
980 if (TLI->getTypeAction(ICmp->getContext(), SrcVT) !=
984 EVT PromotedVT = TLI->getTypeToTransformTo(ICmp->getContext(), SrcVT);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp918 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { argument
925 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
2494 EVT SrcVT = Src.getValueType(); local
2496 if (SrcVT == MVT::i16) {
2506 assert(SrcVT == MVT::i64 && "operation should be legal");
2531 EVT SrcVT = Src.getValueType(); local
2533 if (SrcVT == MVT::i16) {
2543 assert(SrcVT == MVT::i64 && "operation should be legal");
2700 EVT SrcVT = Src.getValueType(); local
2701 if (Subtarget->has16BitInsts() && SrcVT
2723 EVT SrcVT = Src.getValueType(); local
2985 EVT SrcVT = Src.getValueType(); local
3245 EVT SrcVT = Src.getValueType(); local
3850 EVT SrcVT = Src.getValueType(); local
3875 EVT SrcVT = Src.getValueType(); local
3918 EVT SrcVT = Src.getValueType(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp695 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy()); local
696 if (!DstVT || !SrcVT)
700 unsigned SrcNumElems = cast<FixedVectorType>(SrcVT)->getNumElements();
732 auto *MidTy = FixedVectorType::get(SrcVT->getElementType(), FanIn);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2621 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2622 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2631 EVT DestVT, EVT SrcVT) const {
2632 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2634 return isFPExtFree(DestVT, SrcVT);
2704 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, argument

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