Lines Matching refs:SrcVT
918 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
925 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
2494 EVT SrcVT = Src.getValueType();
2496 if (SrcVT == MVT::i16) {
2506 assert(SrcVT == MVT::i64 && "operation should be legal");
2531 EVT SrcVT = Src.getValueType();
2533 if (SrcVT == MVT::i16) {
2543 assert(SrcVT == MVT::i64 && "operation should be legal");
2700 EVT SrcVT = Src.getValueType();
2701 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2723 EVT SrcVT = Src.getValueType();
2724 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2985 EVT SrcVT = Src.getValueType();
2986 if (SrcVT.bitsGE(ExtVT)) {
2987 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);
3245 EVT SrcVT = Src.getValueType();
3246 if (SrcVT.getScalarSizeInBits() > 32 &&
3850 EVT SrcVT = Src.getValueType();
3853 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,
3854 DAG.getConstant(0x8000, SL, SrcVT));
3875 EVT SrcVT = Src.getValueType();
3878 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,
3879 DAG.getConstant(0x7fff, SL, SrcVT));
3918 EVT SrcVT = Src.getValueType();
3921 if (SrcVT.getVectorNumElements() == NElts) {
3926 for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {