Searched refs:CSR_WRITE_1 (Results 1 - 25 of 31) sorted by relevance

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/freebsd-13-stable/sys/dev/vge/
H A Dif_vge.c255 CSR_WRITE_1(sc, VGE_EEADDR, addr);
312 CSR_WRITE_1(sc, VGE_MIICMD, 0);
331 CSR_WRITE_1(sc, VGE_MIICMD, 0);
332 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
347 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
373 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
406 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
444 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
446 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
450 CSR_WRITE_1(s
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H A Dif_vgevar.h223 #define CSR_WRITE_1(sc, reg, val) \ macro
234 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
241 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd-13-stable/sys/dev/vr/
H A Dif_vr.c252 CSR_WRITE_1(sc, VR_MIIADDR, reg);
275 CSR_WRITE_1(sc, VR_MIIADDR, reg);
346 CSR_WRITE_1(sc, VR_CR1, cr1);
361 CSR_WRITE_1(sc, VR_FLOWCR1, fc);
369 CSR_WRITE_1(sc, VR_MISC_CR0, fc);
388 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
390 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
392 CSR_WRITE_1(sc, VR_CAMCTL, 0);
403 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
405 CSR_WRITE_1(s
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H A Dif_vrreg.h753 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->vr_res, reg, val) macro
758 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
759 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd-13-stable/sys/dev/re/
H A Dif_re.c359 CSR_WRITE_1(sc, RL_EECMD, \
363 CSR_WRITE_1(sc, RL_EECMD, \
738 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
749 CSR_WRITE_1(sc, 0x82, 1);
1324 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1327 CSR_WRITE_1(sc, RL_CFG2, cfg);
1328 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1361 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1366 CSR_WRITE_1(sc, RL_CFG2, cfg);
1368 CSR_WRITE_1(s
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/freebsd-13-stable/sys/dev/rl/
H A Dif_rl.c268 CSR_WRITE_1(sc, RL_EECMD, \
272 CSR_WRITE_1(sc, RL_EECMD, \
312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
319 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
386 CSR_WRITE_1(sc, RL_MII, val);
572 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
1719 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1724 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1737 CSR_WRITE_1(s
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H A Dif_rlreg.h952 #define CSR_WRITE_1(sc, reg, val) \ macro
966 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
969 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
/freebsd-13-stable/sys/dev/msk/
H A Dif_msk.c514 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
1257 CSR_WRITE_1(sc, B0_POWER_CTRL,
1273 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1341 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1342 CSR_WRITE_1(sc, B0_POWER_CTRL,
1374 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1386 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1423 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1424 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1443 CSR_WRITE_1(s
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H A Dif_mskreg.h2129 #define CSR_WRITE_1(sc, reg, val) \ macro
2165 CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))
/freebsd-13-stable/sys/dev/fxp/
H A Dif_fxpvar.h249 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val) macro
H A Dif_fxp.c356 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
359 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
502 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
923 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
1023 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1120 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1706 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1752 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
2211 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2435 CSR_WRITE_1(s
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/freebsd-13-stable/sys/dev/ipw/
H A Dif_ipwreg.h336 #define CSR_WRITE_1(sc, reg, val) \ macro
362 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
/freebsd-13-stable/sys/dev/ste/
H A Dif_ste.c199 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
202 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
232 CSR_WRITE_1(sc, STE_PHYCTL, val);
456 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
1541 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1550 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
1553 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1559 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1576 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1645 CSR_WRITE_1(s
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H A Dif_stereg.h487 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd-13-stable/sys/dev/stge/
H A Dif_stge.c277 CSR_WRITE_1(sc, STGE_PhyCtrl, val);
998 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1041 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1963 CSR_WRITE_1(sc, STGE_PhySet, v);
2058 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2061 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2067 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2068 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2074 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2075 CSR_WRITE_1(s
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H A Dif_stgereg.h94 #define CSR_WRITE_1(_sc, reg, val) \ macro
/freebsd-13-stable/sys/dev/iwi/
H A Dif_iwireg.h586 #define CSR_WRITE_1(sc, reg, val) \ macro
604 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/freebsd-13-stable/sys/dev/alc/
H A Dif_alcvar.h266 #define CSR_WRITE_1(_sc, reg, val) \ macro
/freebsd-13-stable/sys/dev/ale/
H A Dif_alevar.h235 #define CSR_WRITE_1(_sc, reg, val) \ macro
/freebsd-13-stable/sys/dev/xl/
H A Dif_xl.c473 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
814 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
818 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
2109 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2123 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2146 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2718 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2759 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2799 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2832 CSR_WRITE_1(s
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H A Dif_xlreg.h658 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd-13-stable/sys/dev/my/
H A Dif_myreg.h394 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd-13-stable/sys/dev/netmap/
H A Dif_re_netmap.h142 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
/freebsd-13-stable/sys/dev/an/
H A Dif_anreg.h54 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->port_res, reg, val) macro
/freebsd-13-stable/sys/dev/lge/
H A Dif_lgereg.h546 #define CSR_WRITE_1(sc, reg, val) \ macro

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