1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#include <sys/cdefs.h> 36__FBSDID("$FreeBSD$"); 37 38#ifdef HAVE_KERNEL_OPTION_HEADERS 39#include "opt_device_polling.h" 40#endif 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/bus.h> 45#include <sys/endian.h> 46#include <sys/kernel.h> 47#include <sys/lock.h> 48#include <sys/malloc.h> 49#include <sys/mbuf.h> 50#include <sys/module.h> 51#include <sys/rman.h> 52#include <sys/socket.h> 53#include <sys/sockio.h> 54#include <sys/sysctl.h> 55 56#include <net/bpf.h> 57#include <net/if.h> 58#include <net/if_var.h> 59#include <net/if_arp.h> 60#include <net/ethernet.h> 61#include <net/if_dl.h> 62#include <net/if_media.h> 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#include <machine/bus.h> 67#include <machine/resource.h> 68 69#include <dev/mii/mii.h> 70#include <dev/mii/mii_bitbang.h> 71#include <dev/mii/miivar.h> 72 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/ste/if_stereg.h> 77 78/* "device miibus" required. See GENERIC if you get errors here. */ 79#include "miibus_if.h" 80 81MODULE_DEPEND(ste, pci, 1, 1, 1); 82MODULE_DEPEND(ste, ether, 1, 1, 1); 83MODULE_DEPEND(ste, miibus, 1, 1, 1); 84 85/* Define to show Tx error status. */ 86#define STE_SHOW_TXERRORS 87 88/* 89 * Various supported device vendors/types and their names. 90 */ 91static const struct ste_type ste_devs[] = { 92 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 93 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 94 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 95 { 0, 0, NULL } 96}; 97 98static int ste_attach(device_t); 99static int ste_detach(device_t); 100static int ste_probe(device_t); 101static int ste_resume(device_t); 102static int ste_shutdown(device_t); 103static int ste_suspend(device_t); 104 105static int ste_dma_alloc(struct ste_softc *); 106static void ste_dma_free(struct ste_softc *); 107static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 108static int ste_eeprom_wait(struct ste_softc *); 109static int ste_encap(struct ste_softc *, struct mbuf **, 110 struct ste_chain *); 111static int ste_ifmedia_upd(struct ifnet *); 112static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 113static void ste_init(void *); 114static void ste_init_locked(struct ste_softc *); 115static int ste_init_rx_list(struct ste_softc *); 116static void ste_init_tx_list(struct ste_softc *); 117static void ste_intr(void *); 118static int ste_ioctl(struct ifnet *, u_long, caddr_t); 119static uint32_t ste_mii_bitbang_read(device_t); 120static void ste_mii_bitbang_write(device_t, uint32_t); 121static int ste_miibus_readreg(device_t, int, int); 122static void ste_miibus_statchg(device_t); 123static int ste_miibus_writereg(device_t, int, int, int); 124static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 125static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int); 126static void ste_reset(struct ste_softc *); 127static void ste_restart_tx(struct ste_softc *); 128static int ste_rxeof(struct ste_softc *, int); 129static void ste_rxfilter(struct ste_softc *); 130static void ste_setwol(struct ste_softc *); 131static void ste_start(struct ifnet *); 132static void ste_start_locked(struct ifnet *); 133static void ste_stats_clear(struct ste_softc *); 134static void ste_stats_update(struct ste_softc *); 135static void ste_stop(struct ste_softc *); 136static void ste_sysctl_node(struct ste_softc *); 137static void ste_tick(void *); 138static void ste_txeoc(struct ste_softc *); 139static void ste_txeof(struct ste_softc *); 140static void ste_wait(struct ste_softc *); 141static void ste_watchdog(struct ste_softc *); 142 143/* 144 * MII bit-bang glue 145 */ 146static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 147 ste_mii_bitbang_read, 148 ste_mii_bitbang_write, 149 { 150 STE_PHYCTL_MDATA, /* MII_BIT_MDO */ 151 STE_PHYCTL_MDATA, /* MII_BIT_MDI */ 152 STE_PHYCTL_MCLK, /* MII_BIT_MDC */ 153 STE_PHYCTL_MDIR, /* MII_BIT_DIR_HOST_PHY */ 154 0, /* MII_BIT_DIR_PHY_HOST */ 155 } 156}; 157 158static device_method_t ste_methods[] = { 159 /* Device interface */ 160 DEVMETHOD(device_probe, ste_probe), 161 DEVMETHOD(device_attach, ste_attach), 162 DEVMETHOD(device_detach, ste_detach), 163 DEVMETHOD(device_shutdown, ste_shutdown), 164 DEVMETHOD(device_suspend, ste_suspend), 165 DEVMETHOD(device_resume, ste_resume), 166 167 /* MII interface */ 168 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 169 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 170 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 171 172 DEVMETHOD_END 173}; 174 175static driver_t ste_driver = { 176 "ste", 177 ste_methods, 178 sizeof(struct ste_softc) 179}; 180 181static devclass_t ste_devclass; 182 183DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 184DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 185 186#define STE_SETBIT4(sc, reg, x) \ 187 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 188 189#define STE_CLRBIT4(sc, reg, x) \ 190 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 191 192#define STE_SETBIT2(sc, reg, x) \ 193 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 194 195#define STE_CLRBIT2(sc, reg, x) \ 196 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 197 198#define STE_SETBIT1(sc, reg, x) \ 199 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 200 201#define STE_CLRBIT1(sc, reg, x) \ 202 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 203 204/* 205 * Read the MII serial port for the MII bit-bang module. 206 */ 207static uint32_t 208ste_mii_bitbang_read(device_t dev) 209{ 210 struct ste_softc *sc; 211 uint32_t val; 212 213 sc = device_get_softc(dev); 214 215 val = CSR_READ_1(sc, STE_PHYCTL); 216 CSR_BARRIER(sc, STE_PHYCTL, 1, 217 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 218 219 return (val); 220} 221 222/* 223 * Write the MII serial port for the MII bit-bang module. 224 */ 225static void 226ste_mii_bitbang_write(device_t dev, uint32_t val) 227{ 228 struct ste_softc *sc; 229 230 sc = device_get_softc(dev); 231 232 CSR_WRITE_1(sc, STE_PHYCTL, val); 233 CSR_BARRIER(sc, STE_PHYCTL, 1, 234 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 235} 236 237static int 238ste_miibus_readreg(device_t dev, int phy, int reg) 239{ 240 241 return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg)); 242} 243 244static int 245ste_miibus_writereg(device_t dev, int phy, int reg, int data) 246{ 247 248 mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data); 249 250 return (0); 251} 252 253static void 254ste_miibus_statchg(device_t dev) 255{ 256 struct ste_softc *sc; 257 struct mii_data *mii; 258 struct ifnet *ifp; 259 uint16_t cfg; 260 261 sc = device_get_softc(dev); 262 263 mii = device_get_softc(sc->ste_miibus); 264 ifp = sc->ste_ifp; 265 if (mii == NULL || ifp == NULL || 266 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 267 return; 268 269 sc->ste_flags &= ~STE_FLAG_LINK; 270 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 271 (IFM_ACTIVE | IFM_AVALID)) { 272 switch (IFM_SUBTYPE(mii->mii_media_active)) { 273 case IFM_10_T: 274 case IFM_100_TX: 275 case IFM_100_FX: 276 case IFM_100_T4: 277 sc->ste_flags |= STE_FLAG_LINK; 278 default: 279 break; 280 } 281 } 282 283 /* Program MACs with resolved speed/duplex/flow-control. */ 284 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 285 cfg = CSR_READ_2(sc, STE_MACCTL0); 286 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 287 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 288 /* 289 * ST201 data sheet says driver should enable receiving 290 * MAC control frames bit of receive mode register to 291 * receive flow-control frames but the register has no 292 * such bits. In addition the controller has no ability 293 * to send pause frames so it should be handled in 294 * driver. Implementing pause timer handling in driver 295 * layer is not trivial, so don't enable flow-control 296 * here. 297 */ 298 cfg |= STE_MACCTL0_FULLDUPLEX; 299 } 300 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 301 } 302} 303 304static int 305ste_ifmedia_upd(struct ifnet *ifp) 306{ 307 struct ste_softc *sc; 308 struct mii_data *mii; 309 struct mii_softc *miisc; 310 int error; 311 312 sc = ifp->if_softc; 313 STE_LOCK(sc); 314 mii = device_get_softc(sc->ste_miibus); 315 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 316 PHY_RESET(miisc); 317 error = mii_mediachg(mii); 318 STE_UNLOCK(sc); 319 320 return (error); 321} 322 323static void 324ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 325{ 326 struct ste_softc *sc; 327 struct mii_data *mii; 328 329 sc = ifp->if_softc; 330 mii = device_get_softc(sc->ste_miibus); 331 332 STE_LOCK(sc); 333 if ((ifp->if_flags & IFF_UP) == 0) { 334 STE_UNLOCK(sc); 335 return; 336 } 337 mii_pollstat(mii); 338 ifmr->ifm_active = mii->mii_media_active; 339 ifmr->ifm_status = mii->mii_media_status; 340 STE_UNLOCK(sc); 341} 342 343static void 344ste_wait(struct ste_softc *sc) 345{ 346 int i; 347 348 for (i = 0; i < STE_TIMEOUT; i++) { 349 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 350 break; 351 DELAY(1); 352 } 353 354 if (i == STE_TIMEOUT) 355 device_printf(sc->ste_dev, "command never completed!\n"); 356} 357 358/* 359 * The EEPROM is slow: give it time to come ready after issuing 360 * it a command. 361 */ 362static int 363ste_eeprom_wait(struct ste_softc *sc) 364{ 365 int i; 366 367 DELAY(1000); 368 369 for (i = 0; i < 100; i++) { 370 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 371 DELAY(1000); 372 else 373 break; 374 } 375 376 if (i == 100) { 377 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 378 return (1); 379 } 380 381 return (0); 382} 383 384/* 385 * Read a sequence of words from the EEPROM. Note that ethernet address 386 * data is stored in the EEPROM in network byte order. 387 */ 388static int 389ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt) 390{ 391 int err = 0, i; 392 393 if (ste_eeprom_wait(sc)) 394 return (1); 395 396 for (i = 0; i < cnt; i++) { 397 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 398 err = ste_eeprom_wait(sc); 399 if (err) 400 break; 401 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA)); 402 dest++; 403 } 404 405 return (err ? 1 : 0); 406} 407 408static u_int 409ste_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 410{ 411 uint32_t *hashes = arg; 412 int h; 413 414 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0x3F; 415 if (h < 32) 416 hashes[0] |= (1 << h); 417 else 418 hashes[1] |= (1 << (h - 32)); 419 420 return (1); 421} 422 423static void 424ste_rxfilter(struct ste_softc *sc) 425{ 426 struct ifnet *ifp; 427 uint32_t hashes[2] = { 0, 0 }; 428 uint8_t rxcfg; 429 430 STE_LOCK_ASSERT(sc); 431 432 ifp = sc->ste_ifp; 433 rxcfg = CSR_READ_1(sc, STE_RX_MODE); 434 rxcfg |= STE_RXMODE_UNICAST; 435 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH | 436 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC); 437 if (ifp->if_flags & IFF_BROADCAST) 438 rxcfg |= STE_RXMODE_BROADCAST; 439 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 440 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 441 rxcfg |= STE_RXMODE_ALLMULTI; 442 if ((ifp->if_flags & IFF_PROMISC) != 0) 443 rxcfg |= STE_RXMODE_PROMISC; 444 goto chipit; 445 } 446 447 rxcfg |= STE_RXMODE_MULTIHASH; 448 /* Now program new ones. */ 449 if_foreach_llmaddr(ifp, ste_hash_maddr, hashes); 450 451chipit: 452 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 453 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 454 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 455 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 456 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg); 457 CSR_READ_1(sc, STE_RX_MODE); 458} 459 460#ifdef DEVICE_POLLING 461static poll_handler_t ste_poll, ste_poll_locked; 462 463static int 464ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 465{ 466 struct ste_softc *sc = ifp->if_softc; 467 int rx_npkts = 0; 468 469 STE_LOCK(sc); 470 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 471 rx_npkts = ste_poll_locked(ifp, cmd, count); 472 STE_UNLOCK(sc); 473 return (rx_npkts); 474} 475 476static int 477ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 478{ 479 struct ste_softc *sc = ifp->if_softc; 480 int rx_npkts; 481 482 STE_LOCK_ASSERT(sc); 483 484 rx_npkts = ste_rxeof(sc, count); 485 ste_txeof(sc); 486 ste_txeoc(sc); 487 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 488 ste_start_locked(ifp); 489 490 if (cmd == POLL_AND_CHECK_STATUS) { 491 uint16_t status; 492 493 status = CSR_READ_2(sc, STE_ISR_ACK); 494 495 if (status & STE_ISR_STATS_OFLOW) 496 ste_stats_update(sc); 497 498 if (status & STE_ISR_HOSTERR) { 499 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 500 ste_init_locked(sc); 501 } 502 } 503 return (rx_npkts); 504} 505#endif /* DEVICE_POLLING */ 506 507static void 508ste_intr(void *xsc) 509{ 510 struct ste_softc *sc; 511 struct ifnet *ifp; 512 uint16_t intrs, status; 513 514 sc = xsc; 515 STE_LOCK(sc); 516 ifp = sc->ste_ifp; 517 518#ifdef DEVICE_POLLING 519 if (ifp->if_capenable & IFCAP_POLLING) { 520 STE_UNLOCK(sc); 521 return; 522 } 523#endif 524 /* Reading STE_ISR_ACK clears STE_IMR register. */ 525 status = CSR_READ_2(sc, STE_ISR_ACK); 526 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 527 STE_UNLOCK(sc); 528 return; 529 } 530 531 intrs = STE_INTRS; 532 if (status == 0xFFFF || (status & intrs) == 0) 533 goto done; 534 535 if (sc->ste_int_rx_act > 0) { 536 status &= ~STE_ISR_RX_DMADONE; 537 intrs &= ~STE_IMR_RX_DMADONE; 538 } 539 540 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) { 541 ste_rxeof(sc, -1); 542 /* 543 * The controller has no ability to Rx interrupt 544 * moderation feature. Receiving 64 bytes frames 545 * from wire generates too many interrupts which in 546 * turn make system useless to process other useful 547 * things. Fortunately ST201 supports single shot 548 * timer so use the timer to implement Rx interrupt 549 * moderation in driver. This adds more register 550 * access but it greatly reduces number of Rx 551 * interrupts under high network load. 552 */ 553 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 554 (sc->ste_int_rx_mod != 0)) { 555 if ((status & STE_ISR_RX_DMADONE) != 0) { 556 CSR_WRITE_2(sc, STE_COUNTDOWN, 557 STE_TIMER_USECS(sc->ste_int_rx_mod)); 558 intrs &= ~STE_IMR_RX_DMADONE; 559 sc->ste_int_rx_act = 1; 560 } else { 561 intrs |= STE_IMR_RX_DMADONE; 562 sc->ste_int_rx_act = 0; 563 } 564 } 565 } 566 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 567 if ((status & STE_ISR_TX_DMADONE) != 0) 568 ste_txeof(sc); 569 if ((status & STE_ISR_TX_DONE) != 0) 570 ste_txeoc(sc); 571 if ((status & STE_ISR_STATS_OFLOW) != 0) 572 ste_stats_update(sc); 573 if ((status & STE_ISR_HOSTERR) != 0) { 574 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 575 ste_init_locked(sc); 576 STE_UNLOCK(sc); 577 return; 578 } 579 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 580 ste_start_locked(ifp); 581done: 582 /* Re-enable interrupts */ 583 CSR_WRITE_2(sc, STE_IMR, intrs); 584 } 585 STE_UNLOCK(sc); 586} 587 588/* 589 * A frame has been uploaded: pass the resulting mbuf chain up to 590 * the higher level protocols. 591 */ 592static int 593ste_rxeof(struct ste_softc *sc, int count) 594{ 595 struct mbuf *m; 596 struct ifnet *ifp; 597 struct ste_chain_onefrag *cur_rx; 598 uint32_t rxstat; 599 int total_len, rx_npkts; 600 601 ifp = sc->ste_ifp; 602 603 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 604 sc->ste_cdata.ste_rx_list_map, 605 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 606 607 cur_rx = sc->ste_cdata.ste_rx_head; 608 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 609 cur_rx = cur_rx->ste_next) { 610 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 611 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 612 break; 613#ifdef DEVICE_POLLING 614 if (ifp->if_capenable & IFCAP_POLLING) { 615 if (count == 0) 616 break; 617 count--; 618 } 619#endif 620 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 621 break; 622 /* 623 * If an error occurs, update stats, clear the 624 * status word and leave the mbuf cluster in place: 625 * it should simply get re-used next time this descriptor 626 * comes up in the ring. 627 */ 628 if (rxstat & STE_RXSTAT_FRAME_ERR) { 629 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 630 cur_rx->ste_ptr->ste_status = 0; 631 continue; 632 } 633 634 /* No errors; receive the packet. */ 635 m = cur_rx->ste_mbuf; 636 total_len = STE_RX_BYTES(rxstat); 637 638 /* 639 * Try to conjure up a new mbuf cluster. If that 640 * fails, it means we have an out of memory condition and 641 * should leave the buffer in place and continue. This will 642 * result in a lost packet, but there's little else we 643 * can do in this situation. 644 */ 645 if (ste_newbuf(sc, cur_rx) != 0) { 646 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 647 cur_rx->ste_ptr->ste_status = 0; 648 continue; 649 } 650 651 m->m_pkthdr.rcvif = ifp; 652 m->m_pkthdr.len = m->m_len = total_len; 653 654 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 655 STE_UNLOCK(sc); 656 (*ifp->if_input)(ifp, m); 657 STE_LOCK(sc); 658 } 659 660 if (rx_npkts > 0) { 661 sc->ste_cdata.ste_rx_head = cur_rx; 662 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 663 sc->ste_cdata.ste_rx_list_map, 664 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 665 } 666 667 return (rx_npkts); 668} 669 670static void 671ste_txeoc(struct ste_softc *sc) 672{ 673 uint16_t txstat; 674 struct ifnet *ifp; 675 676 STE_LOCK_ASSERT(sc); 677 678 ifp = sc->ste_ifp; 679 680 /* 681 * STE_TX_STATUS register implements a queue of up to 31 682 * transmit status byte. Writing an arbitrary value to the 683 * register will advance the queue to the next transmit 684 * status byte. This means if driver does not read 685 * STE_TX_STATUS register after completing sending more 686 * than 31 frames the controller would be stalled so driver 687 * should re-wake the Tx MAC. This is the most severe 688 * limitation of ST201 based controller. 689 */ 690 for (;;) { 691 txstat = CSR_READ_2(sc, STE_TX_STATUS); 692 if ((txstat & STE_TXSTATUS_TXDONE) == 0) 693 break; 694 if ((txstat & (STE_TXSTATUS_UNDERRUN | 695 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR | 696 STE_TXSTATUS_STATSOFLOW)) != 0) { 697 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 698#ifdef STE_SHOW_TXERRORS 699 device_printf(sc->ste_dev, "TX error : 0x%b\n", 700 txstat & 0xFF, STE_ERR_BITS); 701#endif 702 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 && 703 sc->ste_tx_thresh < STE_PACKET_SIZE) { 704 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 705 if (sc->ste_tx_thresh > STE_PACKET_SIZE) 706 sc->ste_tx_thresh = STE_PACKET_SIZE; 707 device_printf(sc->ste_dev, 708 "TX underrun, increasing TX" 709 " start threshold to %d bytes\n", 710 sc->ste_tx_thresh); 711 /* Make sure to disable active DMA cycles. */ 712 STE_SETBIT4(sc, STE_DMACTL, 713 STE_DMACTL_TXDMA_STALL); 714 ste_wait(sc); 715 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 716 ste_init_locked(sc); 717 break; 718 } 719 /* Restart Tx. */ 720 ste_restart_tx(sc); 721 } 722 /* 723 * Advance to next status and ACK TxComplete 724 * interrupt. ST201 data sheet was wrong here, to 725 * get next Tx status, we have to write both 726 * STE_TX_STATUS and STE_TX_FRAMEID register. 727 * Otherwise controller returns the same status 728 * as well as not acknowledge Tx completion 729 * interrupt. 730 */ 731 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 732 } 733} 734 735static void 736ste_tick(void *arg) 737{ 738 struct ste_softc *sc; 739 struct mii_data *mii; 740 741 sc = (struct ste_softc *)arg; 742 743 STE_LOCK_ASSERT(sc); 744 745 mii = device_get_softc(sc->ste_miibus); 746 mii_tick(mii); 747 /* 748 * ukphy(4) does not seem to generate CB that reports 749 * resolved link state so if we know we lost a link, 750 * explicitly check the link state. 751 */ 752 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 753 ste_miibus_statchg(sc->ste_dev); 754 /* 755 * Because we are not generating Tx completion 756 * interrupt for every frame, reclaim transmitted 757 * buffers here. 758 */ 759 ste_txeof(sc); 760 ste_txeoc(sc); 761 ste_stats_update(sc); 762 ste_watchdog(sc); 763 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 764} 765 766static void 767ste_txeof(struct ste_softc *sc) 768{ 769 struct ifnet *ifp; 770 struct ste_chain *cur_tx; 771 uint32_t txstat; 772 int idx; 773 774 STE_LOCK_ASSERT(sc); 775 776 ifp = sc->ste_ifp; 777 idx = sc->ste_cdata.ste_tx_cons; 778 if (idx == sc->ste_cdata.ste_tx_prod) 779 return; 780 781 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 782 sc->ste_cdata.ste_tx_list_map, 783 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 784 785 while (idx != sc->ste_cdata.ste_tx_prod) { 786 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 787 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 788 if ((txstat & STE_TXCTL_DMADONE) == 0) 789 break; 790 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 791 BUS_DMASYNC_POSTWRITE); 792 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 793 KASSERT(cur_tx->ste_mbuf != NULL, 794 ("%s: freeing NULL mbuf!\n", __func__)); 795 m_freem(cur_tx->ste_mbuf); 796 cur_tx->ste_mbuf = NULL; 797 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 798 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 799 sc->ste_cdata.ste_tx_cnt--; 800 STE_INC(idx, STE_TX_LIST_CNT); 801 } 802 803 sc->ste_cdata.ste_tx_cons = idx; 804 if (sc->ste_cdata.ste_tx_cnt == 0) 805 sc->ste_timer = 0; 806} 807 808static void 809ste_stats_clear(struct ste_softc *sc) 810{ 811 812 STE_LOCK_ASSERT(sc); 813 814 /* Rx stats. */ 815 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); 816 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); 817 CSR_READ_2(sc, STE_STAT_RX_FRAMES); 818 CSR_READ_1(sc, STE_STAT_RX_BCAST); 819 CSR_READ_1(sc, STE_STAT_RX_MCAST); 820 CSR_READ_1(sc, STE_STAT_RX_LOST); 821 /* Tx stats. */ 822 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO); 823 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI); 824 CSR_READ_2(sc, STE_STAT_TX_FRAMES); 825 CSR_READ_1(sc, STE_STAT_TX_BCAST); 826 CSR_READ_1(sc, STE_STAT_TX_MCAST); 827 CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 828 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 829 CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 830 CSR_READ_1(sc, STE_STAT_LATE_COLLS); 831 CSR_READ_1(sc, STE_STAT_TX_DEFER); 832 CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 833 CSR_READ_1(sc, STE_STAT_TX_ABORT); 834} 835 836static void 837ste_stats_update(struct ste_softc *sc) 838{ 839 struct ifnet *ifp; 840 struct ste_hw_stats *stats; 841 uint32_t val; 842 843 STE_LOCK_ASSERT(sc); 844 845 ifp = sc->ste_ifp; 846 stats = &sc->ste_stats; 847 /* Rx stats. */ 848 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) | 849 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16; 850 val &= 0x000FFFFF; 851 stats->rx_bytes += val; 852 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES); 853 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST); 854 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST); 855 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST); 856 /* Tx stats. */ 857 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) | 858 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16; 859 val &= 0x000FFFFF; 860 stats->tx_bytes += val; 861 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES); 862 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST); 863 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST); 864 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 865 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 866 stats->tx_single_colls += val; 867 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 868 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 869 stats->tx_multi_colls += val; 870 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 871 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS); 872 stats->tx_late_colls += val; 873 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 874 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER); 875 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 876 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT); 877} 878 879/* 880 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 881 * IDs against our list and return a device name if we find a match. 882 */ 883static int 884ste_probe(device_t dev) 885{ 886 const struct ste_type *t; 887 888 t = ste_devs; 889 890 while (t->ste_name != NULL) { 891 if ((pci_get_vendor(dev) == t->ste_vid) && 892 (pci_get_device(dev) == t->ste_did)) { 893 device_set_desc(dev, t->ste_name); 894 return (BUS_PROBE_DEFAULT); 895 } 896 t++; 897 } 898 899 return (ENXIO); 900} 901 902/* 903 * Attach the interface. Allocate softc structures, do ifmedia 904 * setup and ethernet/BPF attach. 905 */ 906static int 907ste_attach(device_t dev) 908{ 909 struct ste_softc *sc; 910 struct ifnet *ifp; 911 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 912 int error = 0, phy, pmc, prefer_iomap, rid; 913 914 sc = device_get_softc(dev); 915 sc->ste_dev = dev; 916 917 /* 918 * Only use one PHY since this chip reports multiple 919 * Note on the DFE-550 the PHY is at 1 on the DFE-580 920 * it is at 0 & 1. It is rev 0x12. 921 */ 922 if (pci_get_vendor(dev) == DL_VENDORID && 923 pci_get_device(dev) == DL_DEVICEID_DL10050 && 924 pci_get_revid(dev) == 0x12 ) 925 sc->ste_flags |= STE_FLAG_ONE_PHY; 926 927 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 928 MTX_DEF); 929 /* 930 * Map control/status registers. 931 */ 932 pci_enable_busmaster(dev); 933 934 /* 935 * Prefer memory space register mapping over IO space but use 936 * IO space for a device that is known to have issues on memory 937 * mapping. 938 */ 939 prefer_iomap = 0; 940 if (pci_get_device(dev) == ST_DEVICEID_ST201_1) 941 prefer_iomap = 1; 942 else 943 resource_int_value(device_get_name(sc->ste_dev), 944 device_get_unit(sc->ste_dev), "prefer_iomap", 945 &prefer_iomap); 946 if (prefer_iomap == 0) { 947 sc->ste_res_id = PCIR_BAR(1); 948 sc->ste_res_type = SYS_RES_MEMORY; 949 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 950 &sc->ste_res_id, RF_ACTIVE); 951 } 952 if (prefer_iomap || sc->ste_res == NULL) { 953 sc->ste_res_id = PCIR_BAR(0); 954 sc->ste_res_type = SYS_RES_IOPORT; 955 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 956 &sc->ste_res_id, RF_ACTIVE); 957 } 958 if (sc->ste_res == NULL) { 959 device_printf(dev, "couldn't map ports/memory\n"); 960 error = ENXIO; 961 goto fail; 962 } 963 964 /* Allocate interrupt */ 965 rid = 0; 966 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 967 RF_SHAREABLE | RF_ACTIVE); 968 969 if (sc->ste_irq == NULL) { 970 device_printf(dev, "couldn't map interrupt\n"); 971 error = ENXIO; 972 goto fail; 973 } 974 975 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 976 977 /* Reset the adapter. */ 978 ste_reset(sc); 979 980 /* 981 * Get station address from the EEPROM. 982 */ 983 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) { 984 device_printf(dev, "failed to read station address\n"); 985 error = ENXIO; 986 goto fail; 987 } 988 ste_sysctl_node(sc); 989 990 if ((error = ste_dma_alloc(sc)) != 0) 991 goto fail; 992 993 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 994 if (ifp == NULL) { 995 device_printf(dev, "can not if_alloc()\n"); 996 error = ENOSPC; 997 goto fail; 998 } 999 1000 /* Do MII setup. */ 1001 phy = MII_PHY_ANY; 1002 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0) 1003 phy = 0; 1004 error = mii_attach(dev, &sc->ste_miibus, ifp, ste_ifmedia_upd, 1005 ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1006 if (error != 0) { 1007 device_printf(dev, "attaching PHYs failed\n"); 1008 goto fail; 1009 } 1010 1011 ifp->if_softc = sc; 1012 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1013 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1014 ifp->if_ioctl = ste_ioctl; 1015 ifp->if_start = ste_start; 1016 ifp->if_init = ste_init; 1017 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1018 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1019 IFQ_SET_READY(&ifp->if_snd); 1020 1021 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1022 1023 /* 1024 * Call MI attach routine. 1025 */ 1026 ether_ifattach(ifp, (uint8_t *)eaddr); 1027 1028 /* 1029 * Tell the upper layer(s) we support long frames. 1030 */ 1031 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1032 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1033 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 1034 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1035 ifp->if_capenable = ifp->if_capabilities; 1036#ifdef DEVICE_POLLING 1037 ifp->if_capabilities |= IFCAP_POLLING; 1038#endif 1039 1040 /* Hook interrupt last to avoid having to lock softc */ 1041 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1042 NULL, ste_intr, sc, &sc->ste_intrhand); 1043 1044 if (error) { 1045 device_printf(dev, "couldn't set up irq\n"); 1046 ether_ifdetach(ifp); 1047 goto fail; 1048 } 1049 1050fail: 1051 if (error) 1052 ste_detach(dev); 1053 1054 return (error); 1055} 1056 1057/* 1058 * Shutdown hardware and free up resources. This can be called any 1059 * time after the mutex has been initialized. It is called in both 1060 * the error case in attach and the normal detach case so it needs 1061 * to be careful about only freeing resources that have actually been 1062 * allocated. 1063 */ 1064static int 1065ste_detach(device_t dev) 1066{ 1067 struct ste_softc *sc; 1068 struct ifnet *ifp; 1069 1070 sc = device_get_softc(dev); 1071 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1072 ifp = sc->ste_ifp; 1073 1074#ifdef DEVICE_POLLING 1075 if (ifp->if_capenable & IFCAP_POLLING) 1076 ether_poll_deregister(ifp); 1077#endif 1078 1079 /* These should only be active if attach succeeded */ 1080 if (device_is_attached(dev)) { 1081 ether_ifdetach(ifp); 1082 STE_LOCK(sc); 1083 ste_stop(sc); 1084 STE_UNLOCK(sc); 1085 callout_drain(&sc->ste_callout); 1086 } 1087 if (sc->ste_miibus) 1088 device_delete_child(dev, sc->ste_miibus); 1089 bus_generic_detach(dev); 1090 1091 if (sc->ste_intrhand) 1092 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1093 if (sc->ste_irq) 1094 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1095 if (sc->ste_res) 1096 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1097 sc->ste_res); 1098 1099 if (ifp) 1100 if_free(ifp); 1101 1102 ste_dma_free(sc); 1103 mtx_destroy(&sc->ste_mtx); 1104 1105 return (0); 1106} 1107 1108struct ste_dmamap_arg { 1109 bus_addr_t ste_busaddr; 1110}; 1111 1112static void 1113ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1114{ 1115 struct ste_dmamap_arg *ctx; 1116 1117 if (error != 0) 1118 return; 1119 1120 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1121 1122 ctx = (struct ste_dmamap_arg *)arg; 1123 ctx->ste_busaddr = segs[0].ds_addr; 1124} 1125 1126static int 1127ste_dma_alloc(struct ste_softc *sc) 1128{ 1129 struct ste_chain *txc; 1130 struct ste_chain_onefrag *rxc; 1131 struct ste_dmamap_arg ctx; 1132 int error, i; 1133 1134 /* Create parent DMA tag. */ 1135 error = bus_dma_tag_create( 1136 bus_get_dma_tag(sc->ste_dev), /* parent */ 1137 1, 0, /* alignment, boundary */ 1138 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1139 BUS_SPACE_MAXADDR, /* highaddr */ 1140 NULL, NULL, /* filter, filterarg */ 1141 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1142 0, /* nsegments */ 1143 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1144 0, /* flags */ 1145 NULL, NULL, /* lockfunc, lockarg */ 1146 &sc->ste_cdata.ste_parent_tag); 1147 if (error != 0) { 1148 device_printf(sc->ste_dev, 1149 "could not create parent DMA tag.\n"); 1150 goto fail; 1151 } 1152 1153 /* Create DMA tag for Tx descriptor list. */ 1154 error = bus_dma_tag_create( 1155 sc->ste_cdata.ste_parent_tag, /* parent */ 1156 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1157 BUS_SPACE_MAXADDR, /* lowaddr */ 1158 BUS_SPACE_MAXADDR, /* highaddr */ 1159 NULL, NULL, /* filter, filterarg */ 1160 STE_TX_LIST_SZ, /* maxsize */ 1161 1, /* nsegments */ 1162 STE_TX_LIST_SZ, /* maxsegsize */ 1163 0, /* flags */ 1164 NULL, NULL, /* lockfunc, lockarg */ 1165 &sc->ste_cdata.ste_tx_list_tag); 1166 if (error != 0) { 1167 device_printf(sc->ste_dev, 1168 "could not create Tx list DMA tag.\n"); 1169 goto fail; 1170 } 1171 1172 /* Create DMA tag for Rx descriptor list. */ 1173 error = bus_dma_tag_create( 1174 sc->ste_cdata.ste_parent_tag, /* parent */ 1175 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1176 BUS_SPACE_MAXADDR, /* lowaddr */ 1177 BUS_SPACE_MAXADDR, /* highaddr */ 1178 NULL, NULL, /* filter, filterarg */ 1179 STE_RX_LIST_SZ, /* maxsize */ 1180 1, /* nsegments */ 1181 STE_RX_LIST_SZ, /* maxsegsize */ 1182 0, /* flags */ 1183 NULL, NULL, /* lockfunc, lockarg */ 1184 &sc->ste_cdata.ste_rx_list_tag); 1185 if (error != 0) { 1186 device_printf(sc->ste_dev, 1187 "could not create Rx list DMA tag.\n"); 1188 goto fail; 1189 } 1190 1191 /* Create DMA tag for Tx buffers. */ 1192 error = bus_dma_tag_create( 1193 sc->ste_cdata.ste_parent_tag, /* parent */ 1194 1, 0, /* alignment, boundary */ 1195 BUS_SPACE_MAXADDR, /* lowaddr */ 1196 BUS_SPACE_MAXADDR, /* highaddr */ 1197 NULL, NULL, /* filter, filterarg */ 1198 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1199 STE_MAXFRAGS, /* nsegments */ 1200 MCLBYTES, /* maxsegsize */ 1201 0, /* flags */ 1202 NULL, NULL, /* lockfunc, lockarg */ 1203 &sc->ste_cdata.ste_tx_tag); 1204 if (error != 0) { 1205 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1206 goto fail; 1207 } 1208 1209 /* Create DMA tag for Rx buffers. */ 1210 error = bus_dma_tag_create( 1211 sc->ste_cdata.ste_parent_tag, /* parent */ 1212 1, 0, /* alignment, boundary */ 1213 BUS_SPACE_MAXADDR, /* lowaddr */ 1214 BUS_SPACE_MAXADDR, /* highaddr */ 1215 NULL, NULL, /* filter, filterarg */ 1216 MCLBYTES, /* maxsize */ 1217 1, /* nsegments */ 1218 MCLBYTES, /* maxsegsize */ 1219 0, /* flags */ 1220 NULL, NULL, /* lockfunc, lockarg */ 1221 &sc->ste_cdata.ste_rx_tag); 1222 if (error != 0) { 1223 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1224 goto fail; 1225 } 1226 1227 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1228 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1229 (void **)&sc->ste_ldata.ste_tx_list, 1230 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1231 &sc->ste_cdata.ste_tx_list_map); 1232 if (error != 0) { 1233 device_printf(sc->ste_dev, 1234 "could not allocate DMA'able memory for Tx list.\n"); 1235 goto fail; 1236 } 1237 ctx.ste_busaddr = 0; 1238 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1239 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1240 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1241 if (error != 0 || ctx.ste_busaddr == 0) { 1242 device_printf(sc->ste_dev, 1243 "could not load DMA'able memory for Tx list.\n"); 1244 goto fail; 1245 } 1246 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1247 1248 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1249 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1250 (void **)&sc->ste_ldata.ste_rx_list, 1251 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1252 &sc->ste_cdata.ste_rx_list_map); 1253 if (error != 0) { 1254 device_printf(sc->ste_dev, 1255 "could not allocate DMA'able memory for Rx list.\n"); 1256 goto fail; 1257 } 1258 ctx.ste_busaddr = 0; 1259 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1260 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1261 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1262 if (error != 0 || ctx.ste_busaddr == 0) { 1263 device_printf(sc->ste_dev, 1264 "could not load DMA'able memory for Rx list.\n"); 1265 goto fail; 1266 } 1267 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1268 1269 /* Create DMA maps for Tx buffers. */ 1270 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1271 txc = &sc->ste_cdata.ste_tx_chain[i]; 1272 txc->ste_ptr = NULL; 1273 txc->ste_mbuf = NULL; 1274 txc->ste_next = NULL; 1275 txc->ste_phys = 0; 1276 txc->ste_map = NULL; 1277 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1278 &txc->ste_map); 1279 if (error != 0) { 1280 device_printf(sc->ste_dev, 1281 "could not create Tx dmamap.\n"); 1282 goto fail; 1283 } 1284 } 1285 /* Create DMA maps for Rx buffers. */ 1286 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1287 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1288 device_printf(sc->ste_dev, 1289 "could not create spare Rx dmamap.\n"); 1290 goto fail; 1291 } 1292 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1293 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1294 rxc->ste_ptr = NULL; 1295 rxc->ste_mbuf = NULL; 1296 rxc->ste_next = NULL; 1297 rxc->ste_map = NULL; 1298 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1299 &rxc->ste_map); 1300 if (error != 0) { 1301 device_printf(sc->ste_dev, 1302 "could not create Rx dmamap.\n"); 1303 goto fail; 1304 } 1305 } 1306 1307fail: 1308 return (error); 1309} 1310 1311static void 1312ste_dma_free(struct ste_softc *sc) 1313{ 1314 struct ste_chain *txc; 1315 struct ste_chain_onefrag *rxc; 1316 int i; 1317 1318 /* Tx buffers. */ 1319 if (sc->ste_cdata.ste_tx_tag != NULL) { 1320 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1321 txc = &sc->ste_cdata.ste_tx_chain[i]; 1322 if (txc->ste_map != NULL) { 1323 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1324 txc->ste_map); 1325 txc->ste_map = NULL; 1326 } 1327 } 1328 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1329 sc->ste_cdata.ste_tx_tag = NULL; 1330 } 1331 /* Rx buffers. */ 1332 if (sc->ste_cdata.ste_rx_tag != NULL) { 1333 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1334 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1335 if (rxc->ste_map != NULL) { 1336 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1337 rxc->ste_map); 1338 rxc->ste_map = NULL; 1339 } 1340 } 1341 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1342 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1343 sc->ste_cdata.ste_rx_sparemap); 1344 sc->ste_cdata.ste_rx_sparemap = NULL; 1345 } 1346 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1347 sc->ste_cdata.ste_rx_tag = NULL; 1348 } 1349 /* Tx descriptor list. */ 1350 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1351 if (sc->ste_ldata.ste_tx_list_paddr != 0) 1352 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1353 sc->ste_cdata.ste_tx_list_map); 1354 if (sc->ste_ldata.ste_tx_list != NULL) 1355 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1356 sc->ste_ldata.ste_tx_list, 1357 sc->ste_cdata.ste_tx_list_map); 1358 sc->ste_ldata.ste_tx_list = NULL; 1359 sc->ste_ldata.ste_tx_list_paddr = 0; 1360 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1361 sc->ste_cdata.ste_tx_list_tag = NULL; 1362 } 1363 /* Rx descriptor list. */ 1364 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1365 if (sc->ste_ldata.ste_rx_list_paddr != 0) 1366 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1367 sc->ste_cdata.ste_rx_list_map); 1368 if (sc->ste_ldata.ste_rx_list != NULL) 1369 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1370 sc->ste_ldata.ste_rx_list, 1371 sc->ste_cdata.ste_rx_list_map); 1372 sc->ste_ldata.ste_rx_list = NULL; 1373 sc->ste_ldata.ste_rx_list_paddr = 0; 1374 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1375 sc->ste_cdata.ste_rx_list_tag = NULL; 1376 } 1377 if (sc->ste_cdata.ste_parent_tag != NULL) { 1378 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1379 sc->ste_cdata.ste_parent_tag = NULL; 1380 } 1381} 1382 1383static int 1384ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1385{ 1386 struct mbuf *m; 1387 bus_dma_segment_t segs[1]; 1388 bus_dmamap_t map; 1389 int error, nsegs; 1390 1391 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1392 if (m == NULL) 1393 return (ENOBUFS); 1394 m->m_len = m->m_pkthdr.len = MCLBYTES; 1395 m_adj(m, ETHER_ALIGN); 1396 1397 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1398 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1399 m_freem(m); 1400 return (error); 1401 } 1402 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1403 1404 if (rxc->ste_mbuf != NULL) { 1405 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1406 BUS_DMASYNC_POSTREAD); 1407 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1408 } 1409 map = rxc->ste_map; 1410 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1411 sc->ste_cdata.ste_rx_sparemap = map; 1412 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1413 BUS_DMASYNC_PREREAD); 1414 rxc->ste_mbuf = m; 1415 rxc->ste_ptr->ste_status = 0; 1416 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1417 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1418 STE_FRAG_LAST); 1419 return (0); 1420} 1421 1422static int 1423ste_init_rx_list(struct ste_softc *sc) 1424{ 1425 struct ste_chain_data *cd; 1426 struct ste_list_data *ld; 1427 int error, i; 1428 1429 sc->ste_int_rx_act = 0; 1430 cd = &sc->ste_cdata; 1431 ld = &sc->ste_ldata; 1432 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1433 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1434 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1435 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1436 if (error != 0) 1437 return (error); 1438 if (i == (STE_RX_LIST_CNT - 1)) { 1439 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1440 ld->ste_rx_list[i].ste_next = 1441 htole32(ld->ste_rx_list_paddr + 1442 (sizeof(struct ste_desc_onefrag) * 0)); 1443 } else { 1444 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1445 ld->ste_rx_list[i].ste_next = 1446 htole32(ld->ste_rx_list_paddr + 1447 (sizeof(struct ste_desc_onefrag) * (i + 1))); 1448 } 1449 } 1450 1451 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1452 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1453 sc->ste_cdata.ste_rx_list_map, 1454 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1455 1456 return (0); 1457} 1458 1459static void 1460ste_init_tx_list(struct ste_softc *sc) 1461{ 1462 struct ste_chain_data *cd; 1463 struct ste_list_data *ld; 1464 int i; 1465 1466 cd = &sc->ste_cdata; 1467 ld = &sc->ste_ldata; 1468 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1469 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1470 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1471 cd->ste_tx_chain[i].ste_mbuf = NULL; 1472 if (i == (STE_TX_LIST_CNT - 1)) { 1473 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1474 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1475 ld->ste_tx_list_paddr + 1476 (sizeof(struct ste_desc) * 0))); 1477 } else { 1478 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1479 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1480 ld->ste_tx_list_paddr + 1481 (sizeof(struct ste_desc) * (i + 1)))); 1482 } 1483 } 1484 1485 cd->ste_last_tx = NULL; 1486 cd->ste_tx_prod = 0; 1487 cd->ste_tx_cons = 0; 1488 cd->ste_tx_cnt = 0; 1489 1490 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1491 sc->ste_cdata.ste_tx_list_map, 1492 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1493} 1494 1495static void 1496ste_init(void *xsc) 1497{ 1498 struct ste_softc *sc; 1499 1500 sc = xsc; 1501 STE_LOCK(sc); 1502 ste_init_locked(sc); 1503 STE_UNLOCK(sc); 1504} 1505 1506static void 1507ste_init_locked(struct ste_softc *sc) 1508{ 1509 struct ifnet *ifp; 1510 struct mii_data *mii; 1511 uint8_t val; 1512 int i; 1513 1514 STE_LOCK_ASSERT(sc); 1515 ifp = sc->ste_ifp; 1516 mii = device_get_softc(sc->ste_miibus); 1517 1518 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1519 return; 1520 1521 ste_stop(sc); 1522 /* Reset the chip to a known state. */ 1523 ste_reset(sc); 1524 1525 /* Init our MAC address */ 1526 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1527 CSR_WRITE_2(sc, STE_PAR0 + i, 1528 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1529 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1530 } 1531 1532 /* Init RX list */ 1533 if (ste_init_rx_list(sc) != 0) { 1534 device_printf(sc->ste_dev, 1535 "initialization failed: no memory for RX buffers\n"); 1536 ste_stop(sc); 1537 return; 1538 } 1539 1540 /* Set RX polling interval */ 1541 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1542 1543 /* Init TX descriptors */ 1544 ste_init_tx_list(sc); 1545 1546 /* Clear and disable WOL. */ 1547 val = CSR_READ_1(sc, STE_WAKE_EVENT); 1548 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 1549 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 1550 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 1551 1552 /* Set the TX freethresh value */ 1553 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1554 1555 /* Set the TX start threshold for best performance. */ 1556 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1557 1558 /* Set the TX reclaim threshold. */ 1559 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1560 1561 /* Accept VLAN length packets */ 1562 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1563 1564 /* Set up the RX filter. */ 1565 ste_rxfilter(sc); 1566 1567 /* Load the address of the RX list. */ 1568 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1569 ste_wait(sc); 1570 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1571 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1572 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1573 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1574 1575 /* Set TX polling interval(defer until we TX first packet). */ 1576 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1577 1578 /* Load address of the TX list */ 1579 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1580 ste_wait(sc); 1581 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1582 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1583 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1584 ste_wait(sc); 1585 /* Select 3.2us timer. */ 1586 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED | 1587 STE_DMACTL_COUNTDOWN_MODE); 1588 1589 /* Enable receiver and transmitter */ 1590 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1591 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1592 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1593 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1594 1595 /* Enable stats counters. */ 1596 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1597 /* Clear stats counters. */ 1598 ste_stats_clear(sc); 1599 1600 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1601 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1602#ifdef DEVICE_POLLING 1603 /* Disable interrupts if we are polling. */ 1604 if (ifp->if_capenable & IFCAP_POLLING) 1605 CSR_WRITE_2(sc, STE_IMR, 0); 1606 else 1607#endif 1608 /* Enable interrupts. */ 1609 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1610 1611 sc->ste_flags &= ~STE_FLAG_LINK; 1612 /* Switch to the current media. */ 1613 mii_mediachg(mii); 1614 1615 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1616 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1617 1618 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1619} 1620 1621static void 1622ste_stop(struct ste_softc *sc) 1623{ 1624 struct ifnet *ifp; 1625 struct ste_chain_onefrag *cur_rx; 1626 struct ste_chain *cur_tx; 1627 uint32_t val; 1628 int i; 1629 1630 STE_LOCK_ASSERT(sc); 1631 ifp = sc->ste_ifp; 1632 1633 callout_stop(&sc->ste_callout); 1634 sc->ste_timer = 0; 1635 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1636 1637 CSR_WRITE_2(sc, STE_IMR, 0); 1638 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1639 /* Stop pending DMA. */ 1640 val = CSR_READ_4(sc, STE_DMACTL); 1641 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1642 CSR_WRITE_4(sc, STE_DMACTL, val); 1643 ste_wait(sc); 1644 /* Disable auto-polling. */ 1645 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1646 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1647 /* Nullify DMA address to stop any further DMA. */ 1648 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1649 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1650 /* Stop TX/RX MAC. */ 1651 val = CSR_READ_2(sc, STE_MACCTL1); 1652 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1653 STE_MACCTL1_STATS_DISABLE; 1654 CSR_WRITE_2(sc, STE_MACCTL1, val); 1655 for (i = 0; i < STE_TIMEOUT; i++) { 1656 DELAY(10); 1657 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1658 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1659 break; 1660 } 1661 if (i == STE_TIMEOUT) 1662 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1663 /* Acknowledge any pending interrupts. */ 1664 CSR_READ_2(sc, STE_ISR_ACK); 1665 ste_stats_update(sc); 1666 1667 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1668 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1669 if (cur_rx->ste_mbuf != NULL) { 1670 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1671 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1672 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1673 cur_rx->ste_map); 1674 m_freem(cur_rx->ste_mbuf); 1675 cur_rx->ste_mbuf = NULL; 1676 } 1677 } 1678 1679 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1680 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1681 if (cur_tx->ste_mbuf != NULL) { 1682 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1683 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1684 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1685 cur_tx->ste_map); 1686 m_freem(cur_tx->ste_mbuf); 1687 cur_tx->ste_mbuf = NULL; 1688 } 1689 } 1690} 1691 1692static void 1693ste_reset(struct ste_softc *sc) 1694{ 1695 uint32_t ctl; 1696 int i; 1697 1698 ctl = CSR_READ_4(sc, STE_ASICCTL); 1699 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET | 1700 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET | 1701 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET | 1702 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET | 1703 STE_ASICCTL_EXTRESET_RESET; 1704 CSR_WRITE_4(sc, STE_ASICCTL, ctl); 1705 CSR_READ_4(sc, STE_ASICCTL); 1706 /* 1707 * Due to the need of accessing EEPROM controller can take 1708 * up to 1ms to complete the global reset. 1709 */ 1710 DELAY(1000); 1711 1712 for (i = 0; i < STE_TIMEOUT; i++) { 1713 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1714 break; 1715 DELAY(10); 1716 } 1717 1718 if (i == STE_TIMEOUT) 1719 device_printf(sc->ste_dev, "global reset never completed\n"); 1720} 1721 1722static void 1723ste_restart_tx(struct ste_softc *sc) 1724{ 1725 uint16_t mac; 1726 int i; 1727 1728 for (i = 0; i < STE_TIMEOUT; i++) { 1729 mac = CSR_READ_2(sc, STE_MACCTL1); 1730 mac |= STE_MACCTL1_TX_ENABLE; 1731 CSR_WRITE_2(sc, STE_MACCTL1, mac); 1732 mac = CSR_READ_2(sc, STE_MACCTL1); 1733 if ((mac & STE_MACCTL1_TX_ENABLED) != 0) 1734 break; 1735 DELAY(10); 1736 } 1737 1738 if (i == STE_TIMEOUT) 1739 device_printf(sc->ste_dev, "starting Tx failed"); 1740} 1741 1742static int 1743ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1744{ 1745 struct ste_softc *sc; 1746 struct ifreq *ifr; 1747 struct mii_data *mii; 1748 int error = 0, mask; 1749 1750 sc = ifp->if_softc; 1751 ifr = (struct ifreq *)data; 1752 1753 switch (command) { 1754 case SIOCSIFFLAGS: 1755 STE_LOCK(sc); 1756 if ((ifp->if_flags & IFF_UP) != 0) { 1757 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1758 ((ifp->if_flags ^ sc->ste_if_flags) & 1759 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1760 ste_rxfilter(sc); 1761 else 1762 ste_init_locked(sc); 1763 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1764 ste_stop(sc); 1765 sc->ste_if_flags = ifp->if_flags; 1766 STE_UNLOCK(sc); 1767 break; 1768 case SIOCADDMULTI: 1769 case SIOCDELMULTI: 1770 STE_LOCK(sc); 1771 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1772 ste_rxfilter(sc); 1773 STE_UNLOCK(sc); 1774 break; 1775 case SIOCGIFMEDIA: 1776 case SIOCSIFMEDIA: 1777 mii = device_get_softc(sc->ste_miibus); 1778 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1779 break; 1780 case SIOCSIFCAP: 1781 STE_LOCK(sc); 1782 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1783#ifdef DEVICE_POLLING 1784 if ((mask & IFCAP_POLLING) != 0 && 1785 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 1786 ifp->if_capenable ^= IFCAP_POLLING; 1787 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 1788 error = ether_poll_register(ste_poll, ifp); 1789 if (error != 0) { 1790 STE_UNLOCK(sc); 1791 break; 1792 } 1793 /* Disable interrupts. */ 1794 CSR_WRITE_2(sc, STE_IMR, 0); 1795 } else { 1796 error = ether_poll_deregister(ifp); 1797 /* Enable interrupts. */ 1798 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1799 } 1800 } 1801#endif /* DEVICE_POLLING */ 1802 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1803 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1804 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1805 STE_UNLOCK(sc); 1806 break; 1807 default: 1808 error = ether_ioctl(ifp, command, data); 1809 break; 1810 } 1811 1812 return (error); 1813} 1814 1815static int 1816ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1817{ 1818 struct ste_frag *frag; 1819 struct mbuf *m; 1820 struct ste_desc *desc; 1821 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1822 int error, i, nsegs; 1823 1824 STE_LOCK_ASSERT(sc); 1825 M_ASSERTPKTHDR((*m_head)); 1826 1827 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1828 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1829 if (error == EFBIG) { 1830 m = m_collapse(*m_head, M_NOWAIT, STE_MAXFRAGS); 1831 if (m == NULL) { 1832 m_freem(*m_head); 1833 *m_head = NULL; 1834 return (ENOMEM); 1835 } 1836 *m_head = m; 1837 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1838 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1839 if (error != 0) { 1840 m_freem(*m_head); 1841 *m_head = NULL; 1842 return (error); 1843 } 1844 } else if (error != 0) 1845 return (error); 1846 if (nsegs == 0) { 1847 m_freem(*m_head); 1848 *m_head = NULL; 1849 return (EIO); 1850 } 1851 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1852 BUS_DMASYNC_PREWRITE); 1853 1854 desc = txc->ste_ptr; 1855 for (i = 0; i < nsegs; i++) { 1856 frag = &desc->ste_frags[i]; 1857 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1858 frag->ste_len = htole32(txsegs[i].ds_len); 1859 } 1860 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1861 /* 1862 * Because we use Tx polling we can't chain multiple 1863 * Tx descriptors here. Otherwise we race with controller. 1864 */ 1865 desc->ste_next = 0; 1866 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0) 1867 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | 1868 STE_TXCTL_DMAINTR); 1869 else 1870 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS); 1871 txc->ste_mbuf = *m_head; 1872 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1873 sc->ste_cdata.ste_tx_cnt++; 1874 1875 return (0); 1876} 1877 1878static void 1879ste_start(struct ifnet *ifp) 1880{ 1881 struct ste_softc *sc; 1882 1883 sc = ifp->if_softc; 1884 STE_LOCK(sc); 1885 ste_start_locked(ifp); 1886 STE_UNLOCK(sc); 1887} 1888 1889static void 1890ste_start_locked(struct ifnet *ifp) 1891{ 1892 struct ste_softc *sc; 1893 struct ste_chain *cur_tx; 1894 struct mbuf *m_head = NULL; 1895 int enq; 1896 1897 sc = ifp->if_softc; 1898 STE_LOCK_ASSERT(sc); 1899 1900 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1901 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1902 return; 1903 1904 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 1905 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1906 /* 1907 * Controller may have cached copy of the last used 1908 * next ptr so we have to reserve one TFD to avoid 1909 * TFD overruns. 1910 */ 1911 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1912 break; 1913 } 1914 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1915 if (m_head == NULL) 1916 break; 1917 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1918 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1919 if (m_head == NULL) 1920 break; 1921 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1922 break; 1923 } 1924 if (sc->ste_cdata.ste_last_tx == NULL) { 1925 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1926 sc->ste_cdata.ste_tx_list_map, 1927 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1928 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1929 ste_wait(sc); 1930 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1931 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1932 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1933 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1934 ste_wait(sc); 1935 } else { 1936 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1937 sc->ste_cdata.ste_last_tx->ste_phys; 1938 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1939 sc->ste_cdata.ste_tx_list_map, 1940 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1941 } 1942 sc->ste_cdata.ste_last_tx = cur_tx; 1943 1944 enq++; 1945 /* 1946 * If there's a BPF listener, bounce a copy of this frame 1947 * to him. 1948 */ 1949 BPF_MTAP(ifp, m_head); 1950 } 1951 1952 if (enq > 0) 1953 sc->ste_timer = STE_TX_TIMEOUT; 1954} 1955 1956static void 1957ste_watchdog(struct ste_softc *sc) 1958{ 1959 struct ifnet *ifp; 1960 1961 ifp = sc->ste_ifp; 1962 STE_LOCK_ASSERT(sc); 1963 1964 if (sc->ste_timer == 0 || --sc->ste_timer) 1965 return; 1966 1967 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1968 if_printf(ifp, "watchdog timeout\n"); 1969 1970 ste_txeof(sc); 1971 ste_txeoc(sc); 1972 ste_rxeof(sc, -1); 1973 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1974 ste_init_locked(sc); 1975 1976 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1977 ste_start_locked(ifp); 1978} 1979 1980static int 1981ste_shutdown(device_t dev) 1982{ 1983 1984 return (ste_suspend(dev)); 1985} 1986 1987static int 1988ste_suspend(device_t dev) 1989{ 1990 struct ste_softc *sc; 1991 1992 sc = device_get_softc(dev); 1993 1994 STE_LOCK(sc); 1995 ste_stop(sc); 1996 ste_setwol(sc); 1997 STE_UNLOCK(sc); 1998 1999 return (0); 2000} 2001 2002static int 2003ste_resume(device_t dev) 2004{ 2005 struct ste_softc *sc; 2006 struct ifnet *ifp; 2007 int pmc; 2008 uint16_t pmstat; 2009 2010 sc = device_get_softc(dev); 2011 STE_LOCK(sc); 2012 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) == 0) { 2013 /* Disable PME and clear PME status. */ 2014 pmstat = pci_read_config(sc->ste_dev, 2015 pmc + PCIR_POWER_STATUS, 2); 2016 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2017 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2018 pci_write_config(sc->ste_dev, 2019 pmc + PCIR_POWER_STATUS, pmstat, 2); 2020 } 2021 } 2022 ifp = sc->ste_ifp; 2023 if ((ifp->if_flags & IFF_UP) != 0) { 2024 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2025 ste_init_locked(sc); 2026 } 2027 STE_UNLOCK(sc); 2028 2029 return (0); 2030} 2031 2032#define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2033 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2034#define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2035 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2036 2037static void 2038ste_sysctl_node(struct ste_softc *sc) 2039{ 2040 struct sysctl_ctx_list *ctx; 2041 struct sysctl_oid_list *child, *parent; 2042 struct sysctl_oid *tree; 2043 struct ste_hw_stats *stats; 2044 2045 stats = &sc->ste_stats; 2046 ctx = device_get_sysctl_ctx(sc->ste_dev); 2047 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev)); 2048 2049 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod", 2050 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation"); 2051 /* Pull in device tunables. */ 2052 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT; 2053 resource_int_value(device_get_name(sc->ste_dev), 2054 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod); 2055 2056 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 2057 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "STE statistics"); 2058 parent = SYSCTL_CHILDREN(tree); 2059 2060 /* Rx statistics. */ 2061 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2062 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 2063 child = SYSCTL_CHILDREN(tree); 2064 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2065 &stats->rx_bytes, "Good octets"); 2066 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2067 &stats->rx_frames, "Good frames"); 2068 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2069 &stats->rx_bcast_frames, "Good broadcast frames"); 2070 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2071 &stats->rx_mcast_frames, "Good multicast frames"); 2072 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames", 2073 &stats->rx_lost_frames, "Lost frames"); 2074 2075 /* Tx statistics. */ 2076 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2077 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 2078 child = SYSCTL_CHILDREN(tree); 2079 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2080 &stats->tx_bytes, "Good octets"); 2081 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2082 &stats->tx_frames, "Good frames"); 2083 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2084 &stats->tx_bcast_frames, "Good broadcast frames"); 2085 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2086 &stats->tx_mcast_frames, "Good multicast frames"); 2087 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs", 2088 &stats->tx_carrsense_errs, "Carrier sense errors"); 2089 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 2090 &stats->tx_single_colls, "Single collisions"); 2091 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 2092 &stats->tx_multi_colls, "Multiple collisions"); 2093 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2094 &stats->tx_late_colls, "Late collisions"); 2095 STE_SYSCTL_STAT_ADD32(ctx, child, "defers", 2096 &stats->tx_frames_defered, "Frames with deferrals"); 2097 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 2098 &stats->tx_excess_defers, "Frames with excessive derferrals"); 2099 STE_SYSCTL_STAT_ADD32(ctx, child, "abort", 2100 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 2101} 2102 2103#undef STE_SYSCTL_STAT_ADD32 2104#undef STE_SYSCTL_STAT_ADD64 2105 2106static void 2107ste_setwol(struct ste_softc *sc) 2108{ 2109 struct ifnet *ifp; 2110 uint16_t pmstat; 2111 uint8_t val; 2112 int pmc; 2113 2114 STE_LOCK_ASSERT(sc); 2115 2116 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) != 0) { 2117 /* Disable WOL. */ 2118 CSR_READ_1(sc, STE_WAKE_EVENT); 2119 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0); 2120 return; 2121 } 2122 2123 ifp = sc->ste_ifp; 2124 val = CSR_READ_1(sc, STE_WAKE_EVENT); 2125 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 2126 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 2127 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2128 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB; 2129 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 2130 /* Request PME. */ 2131 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2); 2132 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2133 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2134 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2135 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2136} 2137