Searched refs:CSR_READ_1 (Results 1 - 25 of 30) sorted by relevance

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/freebsd-13-stable/sys/dev/ste/
H A Dif_ste.c199 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
202 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
215 val = CSR_READ_1(sc, STE_PHYCTL);
433 rxcfg = CSR_READ_1(sc, STE_RX_MODE);
457 CSR_READ_1(sc, STE_RX_MODE);
818 CSR_READ_1(sc, STE_STAT_RX_BCAST);
819 CSR_READ_1(sc, STE_STAT_RX_MCAST);
820 CSR_READ_1(sc, STE_STAT_RX_LOST);
825 CSR_READ_1(sc, STE_STAT_TX_BCAST);
826 CSR_READ_1(s
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H A Dif_stereg.h494 #define CSR_READ_1(sc, reg) \ macro
/freebsd-13-stable/sys/dev/vge/
H A Dif_vgevar.h230 #define CSR_READ_1(sc, reg) \ macro
234 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
241 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
H A Dif_vge.c262 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
316 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
336 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
353 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
381 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
417 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
486 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
524 cfg = CSR_READ_1(sc, VGE_RXCFG);
577 rxcfg = CSR_READ_1(s
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/freebsd-13-stable/sys/dev/re/
H A Dif_re.c360 CSR_READ_1(sc, RL_EECMD) | x)
364 CSR_READ_1(sc, RL_EECMD) & ~x)
414 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
459 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
557 rval = CSR_READ_1(sc, RL_MEDIASTAT);
742 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
1325 cfg = CSR_READ_1(sc, RL_CFG2);
1362 cfg = CSR_READ_1(sc, RL_CFG2);
1559 cfg = CSR_READ_1(sc, sc->rl_cfg1);
1562 cfg = CSR_READ_1(s
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/freebsd-13-stable/sys/dev/vr/
H A Dif_vr.c257 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
281 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
326 cr0 = CSR_READ_1(sc, VR_CR0);
327 cr1 = CSR_READ_1(sc, VR_CR1);
351 fc = CSR_READ_1(sc, VR_FLOWCR1);
364 fc = CSR_READ_1(sc, VR_MISC_CR0);
422 if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0)
486 rxfilt = CSR_READ_1(sc, VR_RXCFG);
548 if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET))
733 if ((CSR_READ_1(s
[all...]
H A Dif_vrreg.h756 #define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg) macro
758 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
759 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd-13-stable/sys/dev/rl/
H A Dif_rl.c269 CSR_READ_1(sc, RL_EECMD) | x)
273 CSR_READ_1(sc, RL_EECMD) & ~x)
327 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
369 val = CSR_READ_1(sc, RL_MII);
426 return (CSR_READ_1(sc, RL_MEDIASTAT));
576 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
780 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1146 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1931 if ((CSR_READ_1(sc, RL_COMMAND) &
2068 v = CSR_READ_1(s
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H A Dif_rlreg.h959 #define CSR_READ_1(sc, reg) \ macro
966 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
969 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
/freebsd-13-stable/sys/dev/fxp/
H A Dif_fxpvar.h246 #define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) macro
H A Dif_fxp.c339 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
342 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
343 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
345 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
346 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
347 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
923 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
1121 CSR_READ_1(sc, FXP_CSR_PMDR));
1698 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1737 while ((statack = CSR_READ_1(s
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/freebsd-13-stable/sys/dev/ipw/
H A Dif_ipwreg.h327 #define CSR_READ_1(sc, reg) \ macro
354 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA))
/freebsd-13-stable/sys/dev/xl/
H A Dif_xl.c458 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
630 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
690 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
819 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
2092 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2315 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2331 CSR_READ_1(sc, XL_W4_BADSSD);
2830 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2956 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2965 if (CSR_READ_1(s
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H A Dif_xlreg.h665 #define CSR_READ_1(sc, reg) \ macro
/freebsd-13-stable/sys/dev/msk/
H A Dif_msk.c1211 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
1673 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1787 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1788 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1826 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1829 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1831 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3418 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3846 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
4101 CSR_READ_1(s
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H A Dif_mskreg.h2136 #define CSR_READ_1(sc, reg) \ macro
2158 CSR_READ_1((sc_if)->msk_softc, (reg))
/freebsd-13-stable/sys/dev/stge/
H A Dif_stge.c259 val = CSR_READ_1(sc, STGE_PhyCtrl);
298 error = CSR_READ_1(sc, STGE_PhyCtrl);
596 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
992 v = CSR_READ_1(sc, STGE_WakeEvent);
1038 v = CSR_READ_1(sc, STGE_WakeEvent);
1960 v = CSR_READ_1(sc, STGE_PhySet);
H A Dif_stgereg.h101 #define CSR_READ_1(_sc, reg) \ macro
/freebsd-13-stable/sys/dev/lge/
H A Dif_lge.c673 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
1003 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1209 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
H A Dif_lgereg.h549 #define CSR_READ_1(sc, reg) \ macro
/freebsd-13-stable/sys/dev/my/
H A Dif_myreg.h401 #define CSR_READ_1(sc, reg) \ macro
H A Dif_my.c858 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
/freebsd-13-stable/sys/dev/an/
H A Dif_anreg.h56 #define CSR_READ_1(sc, reg) bus_read_1(sc->port_res, reg) macro
/freebsd-13-stable/sys/dev/iwi/
H A Dif_iwireg.h573 #define CSR_READ_1(sc, reg) \ macro
/freebsd-13-stable/sys/dev/sk/
H A Dif_skreg.h1287 #define CSR_READ_1(sc, reg) \ macro

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