Searched refs:BR_CC (Results 1 - 25 of 31) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.h29 BR_CC,
H A DBPFISelLowering.cpp71 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
108 setOperationAction(ISD::BR_CC, MVT::i32,
224 case ISD::BR_CC:
543 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
575 case BPFISD::BR_CC:
576 return "BPFISD::BR_CC";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h49 // BR_CC - Used to glue together a conditional branch and comparison
50 BR_CC, enumerator in enum:llvm::LanaiISD::__anon4175
H A DLanaiISelLowering.cpp85 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
180 case ISD::BR_CC:
879 return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
1110 case LanaiISD::BR_CC:
1111 return "LanaiISD::BR_CC";
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h850 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
854 BR_CC, enumerator in enum:llvm::ISD::NodeType
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h60 BR_CC,
H A DMSP430ISelLowering.cpp90 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
91 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
349 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
1138 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1381 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp117 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
205 assert(LHS.getValueType() == MVT::i32 && "Only know how to BR_CC i32");
757 case ISD::BR_CC:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp97 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
98 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
99 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
100 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
696 case ISD::BR_CC:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1033 case ISD::BR_CC: {
1038 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 :
3639 // Expand brcond's setcc into its constituent parts and create a BR_CC
3644 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3658 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3798 case ISD::BR_CC: {
3810 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3812 assert(!NeedInvert && "Don't know how to invert BR_CC!");
3814 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3817 Tmp1 = DAG.getNode(ISD::BR_CC, d
[all...]
H A DSelectionDAGDumper.cpp367 case ISD::BR_CC: return "br_cc";
H A DLegalizeFloatTypes.cpp794 case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
1700 case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break;
1734 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
H A DLegalizeIntegerTypes.cpp1355 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1450 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
3902 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
3944 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1541 // Sparc doesn't have BRCOND either, it has BR_CC.
1545 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1546 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1547 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1548 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1569 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
3033 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1585 // Expand BR_CC and SELECT_CC for all integer and fp types.
1587 setOperationAction(ISD::BR_CC, VT, Expand);
1591 setOperationAction(ISD::BR_CC, VT, Expand);
1594 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1618 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp103 setOperationAction(ISD::BR_CC, XLenVT, Expand);
190 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
207 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp402 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
403 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
404 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
405 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
H A DMipsSEISelLowering.cpp129 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp263 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
264 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
265 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
266 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
267 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
317 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
482 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
517 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
544 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
785 setOperationAction(ISD::BR_CC, MV
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp150 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
151 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
H A DSIISelLowering.cpp268 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
269 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
270 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
271 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
272 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
552 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
590 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp217 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp92 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp782 setTargetDAGCombine(ISD::BR_CC);
1362 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1364 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1365 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1366 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
9729 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
15575 assert(N->getOpcode() == ISD::BR_CC && "Expected BRCOND or BR_CC!");
15933 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp383 setOperationAction(ISD::BR_CC, VT, Expand);

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