/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.h | 29 BR_CC,
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H A D | BPFISelLowering.cpp | 71 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 108 setOperationAction(ISD::BR_CC, MVT::i32, 224 case ISD::BR_CC: 543 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, 575 case BPFISD::BR_CC: 576 return "BPFISD::BR_CC";
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.h | 49 // BR_CC - Used to glue together a conditional branch and comparison 50 BR_CC, enumerator in enum:llvm::LanaiISD::__anon4175
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H A D | LanaiISelLowering.cpp | 85 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 180 case ISD::BR_CC: 879 return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest, 1110 case LanaiISD::BR_CC: 1111 return "LanaiISD::BR_CC";
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 850 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 854 BR_CC, enumerator in enum:llvm::ISD::NodeType
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 60 BR_CC,
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H A D | MSP430ISelLowering.cpp | 90 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 91 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 349 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 1138 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), 1381 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 117 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 205 assert(LHS.getValueType() == MVT::i32 && "Only know how to BR_CC i32"); 757 case ISD::BR_CC:
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 97 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 98 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 99 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 100 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 696 case ISD::BR_CC:
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 1033 case ISD::BR_CC: { 1038 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 3639 // Expand brcond's setcc into its constituent parts and create a BR_CC 3644 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3658 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3798 case ISD::BR_CC: { 3810 assert(Legalized && "Can't legalize BR_CC with legal condition!"); 3812 assert(!NeedInvert && "Don't know how to invert BR_CC!"); 3814 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC 3817 Tmp1 = DAG.getNode(ISD::BR_CC, d [all...] |
H A D | SelectionDAGDumper.cpp | 367 case ISD::BR_CC: return "br_cc";
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H A D | LegalizeFloatTypes.cpp | 794 case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break; 1700 case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break; 1734 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
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H A D | LegalizeIntegerTypes.cpp | 1355 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 1450 /// shared among BR_CC, SELECT_CC, and SETCC handlers. 3902 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 3944 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1541 // Sparc doesn't have BRCOND either, it has BR_CC. 1545 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 1546 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 1547 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 1548 setOperationAction(ISD::BR_CC, MVT::f128, Custom); 1569 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 3033 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1585 // Expand BR_CC and SELECT_CC for all integer and fp types. 1587 setOperationAction(ISD::BR_CC, VT, Expand); 1591 setOperationAction(ISD::BR_CC, VT, Expand); 1594 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 1618 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 103 setOperationAction(ISD::BR_CC, XLenVT, Expand); 190 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 207 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 402 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 403 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 404 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 405 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
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H A D | MipsSEISelLowering.cpp | 129 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 263 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 264 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 265 setOperationAction(ISD::BR_CC, MVT::f16, Custom); 266 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 267 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 317 setOperationAction(ISD::BR_CC, MVT::f128, Custom); 482 setOperationAction(ISD::BR_CC, MVT::f16, Promote); 517 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand); 544 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand); 785 setOperationAction(ISD::BR_CC, MV [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 150 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 151 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
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H A D | SIISelLowering.cpp | 268 setOperationAction(ISD::BR_CC, MVT::i1, Expand); 269 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 270 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 271 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 272 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 552 setOperationAction(ISD::BR_CC, MVT::i16, Expand); 590 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 217 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 92 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 782 setTargetDAGCombine(ISD::BR_CC); 1362 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 1364 setOperationAction(ISD::BR_CC, MVT::f16, Custom); 1365 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 1366 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 9729 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 15575 assert(N->getOpcode() == ISD::BR_CC && "Expected BRCOND or BR_CC!"); 15933 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 383 setOperationAction(ISD::BR_CC, VT, Expand);
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