Searched refs:AMDGPU (Results 1 - 25 of 117) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp9 #include "AMDGPU.h"
62 case AMDGPU::COPY:
63 case AMDGPU::S_MOV_B64:
64 case AMDGPU::S_MOV_B64_term:
65 case AMDGPU::S_MOV_B32:
66 case AMDGPU::S_MOV_B32_term: {
69 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC))
74 return AMDGPU::NoRegister;
80 case AMDGPU
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H A DSIRegisterInfo.cpp45 : AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour()), ST(ST),
48 assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&
49 getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) &&
50 (getSubRegIndexLaneMask(AMDGPU::lo16) |
51 getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() ==
52 getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() &&
56 RegPressureIgnoredUnits.set(*MCRegUnitIterator(AMDGPU::M0, this));
57 for (auto Reg : AMDGPU::VGPR_HI16RegClass)
104 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
149 Register SIRegisterInfo::getBaseRegister() const { return AMDGPU
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H A DAMDGPURegisterBankInfo.cpp10 /// AMDGPU.
14 /// AMDGPU has unique register bank constraints that require special high level
121 if (Opc == AMDGPU::G_ANYEXT || Opc == AMDGPU::G_ZEXT ||
122 Opc == AMDGPU::G_SEXT) {
129 if (SrcBank == &AMDGPU::VCCRegBank) {
133 assert(NewBank == &AMDGPU::VGPRRegBank);
138 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1);
152 if (Opc == AMDGPU::G_TRUNC) {
155 assert(DstBank != &AMDGPU
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H A DSIInstrInfo.cpp15 #include "AMDGPU.h"
72 namespace AMDGPU { namespace in namespace:llvm
95 : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
117 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
118 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
144 case AMDGPU::V_MOV_B32_e32:
145 case AMDGPU::V_MOV_B32_e64:
146 case AMDGPU::V_MOV_B64_PSEUDO:
147 case AMDGPU
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H A DSIPeepholeSDWA.cpp22 #include "AMDGPU.h"
138 using namespace AMDGPU::SDWA;
334 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) {
335 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
338 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) {
339 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) {
369 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
370 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel);
372 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
376 Src = TII->getNamedOperand(MI, AMDGPU
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H A DSIOptimizeExecMaskingPreRA.cpp15 #include "AMDGPU.h"
72 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
103 const unsigned AndOpc = Wave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
104 const unsigned Andn2Opc = Wave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64;
105 const unsigned CondReg = Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC;
106 const unsigned ExecReg = Wave32 ? AMDGPU
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H A DAMDGPUMacroFusion.cpp1 //===--- AMDGPUMacroFusion.cpp - AMDGPU Macro Fusion ----------------------===//
9 /// \file This file contains the AMDGPU implementation of the DAG scheduling
35 case AMDGPU::V_ADDC_U32_e64:
36 case AMDGPU::V_SUBB_U32_e64:
37 case AMDGPU::V_SUBBREV_U32_e64:
38 case AMDGPU::V_CNDMASK_B32_e64: {
49 AMDGPU::OpName::src2);
H A DGCNDPPCombine.cpp40 #include "AMDGPU.h"
130 auto DPP32 = AMDGPU::getDPPOp32(Op);
132 auto E32 = AMDGPU::getVOPe32(Op);
133 DPP32 = (E32 == -1)? -1 : AMDGPU::getDPPOp32(E32);
149 case AMDGPU::IMPLICIT_DEF:
151 case AMDGPU::COPY:
152 case AMDGPU::V_MOV_B32_e32: {
166 assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
181 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);
186 const int OldIdx = AMDGPU
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H A DSIFoldOperands.cpp11 #include "AMDGPU.h"
143 case AMDGPU::V_MAC_F32_e64:
144 case AMDGPU::V_MAC_F16_e64:
145 case AMDGPU::V_FMAC_F32_e64:
146 case AMDGPU::V_FMAC_F16_e64: {
149 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
151 bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e64 ||
152 Opc == AMDGPU::V_FMAC_F16_e64;
153 bool IsF32 = Opc == AMDGPU
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H A DAMDGPUGlobalISelUtils.h21 namespace AMDGPU { namespace in namespace:llvm
32 getImageNumVAddr(const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr,
33 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode) {
34 const AMDGPU::MIMGDimInfo *DimInfo
35 = AMDGPU::getMIMGDimInfo(ImageDimIntr->Dim);
45 inline int getDMaskIdx(const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode,
52 inline int getImageVAddrIdxBegin(const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode,
H A DAMDGPUArgumentUsageInfo.cpp9 #include "AMDGPU.h"
93 &AMDGPU::SGPR_128RegClass, LLT::vector(4, 32));
97 &AMDGPU::SGPR_64RegClass,
101 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
104 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
107 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
111 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
114 &AMDGPU::SGPR_64RegClass,
118 &AMDGPU::SGPR_64RegClass,
122 &AMDGPU
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H A DSIInsertSkips.cpp16 #include "AMDGPU.h"
110 case AMDGPU::SI_MASK_BRANCH:
137 if (I->getOpcode() == AMDGPU::S_CBRANCH_VCCNZ ||
138 I->getOpcode() == AMDGPU::S_CBRANCH_VCCZ)
146 I->getOpcode() == AMDGPU::S_WAITCNT)
171 BuildMI(MBB, I, DL, TII->get(AMDGPU::EXP_DONE))
173 .addReg(AMDGPU::VGPR0, RegState::Undef)
174 .addReg(AMDGPU::VGPR0, RegState::Undef)
175 .addReg(AMDGPU::VGPR0, RegState::Undef)
176 .addReg(AMDGPU
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H A DSILoadStoreOptimizer.cpp60 #include "AMDGPU.h"
311 return AMDGPU::getMUBUFElements(Opc);
315 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm();
319 return AMDGPU::getMTBUFElements(Opc);
323 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM:
325 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM:
327 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM:
339 switch (AMDGPU::getMUBUFBaseOpcode(Opc)) {
342 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN:
343 case AMDGPU
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H A DAMDGPUInstructionSelector.cpp10 /// AMDGPU.
93 return RB->getID() == AMDGPU::VCCRegBankID;
100 MI.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
131 if (SrcReg == AMDGPU::SCC) {
154 AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32;
158 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
252 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
268 case AMDGPU::sub0:
270 case AMDGPU
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H A DGCNHazardRecognizer.cpp49 MaxLookAhead = MF.getRegInfo().isPhysRegUsed(AMDGPU::AGPR0) ? 18 : 5;
62 return Opcode == AMDGPU::V_DIV_FMAS_F32 || Opcode == AMDGPU::V_DIV_FMAS_F64;
66 return Opcode == AMDGPU::S_GETREG_B32;
70 return Opcode == AMDGPU::S_SETREG_B32 || Opcode == AMDGPU::S_SETREG_IMM32_B32;
74 return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32;
78 return Opcode == AMDGPU::S_RFE_B64;
83 case AMDGPU
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H A DAMDGPUAsmPrinter.cpp1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer --------------------===//
19 #include "AMDGPU.h"
49 using namespace llvm::AMDGPU;
50 using namespace llvm::AMDGPU::HSAMD;
88 static uint32_t getFPMode(AMDGPU::SIModeRegisterDefaults Mode) {
118 return "AMDGPU Assembly Printer";
160 Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
196 return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
337 if (AMDGPU::isGFX10(STI) &&
441 Context.getELFSection(".AMDGPU
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H A DSIFixVGPRCopies.cpp14 #include "AMDGPU.h"
57 case AMDGPU::COPY:
58 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
60 MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
H A DSIPreEmitPeephole.cpp14 #include "AMDGPU.h"
70 const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
71 const unsigned And = IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
72 const unsigned AndN2 = IsWave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64;
139 if (!ReadsCond && A->registerDefIsDead(AMDGPU::SCC) &&
143 bool IsVCCZ = MI.getOpcode() == AMDGPU::S_CBRANCH_VCCZ;
150 MI.setDesc(TII->get(AMDGPU
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUFixupKinds.h1 //===-- AMDGPUFixupKinds.h - AMDGPU Specific Fixup Entries ------*- C++ -*-===//
15 namespace AMDGPU { namespace in namespace:llvm
H A DSIMCCodeEmitter.cpp15 #include "AMDGPU.h"
146 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
182 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
218 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
245 case AMDGPU::OPERAND_REG_IMM_INT32:
246 case AMDGPU::OPERAND_REG_IMM_FP32:
247 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
248 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
249 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
250 case AMDGPU
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/freebsd-13-stable/contrib/llvm-project/lld/ELF/Arch/
H A DAMDGPU.cpp1 //===- AMDGPU.cpp ---------------------------------------------------------===//
24 class AMDGPU final : public TargetInfo {
26 AMDGPU();
36 AMDGPU::AMDGPU() { function in class:AMDGPU
47 uint32_t AMDGPU::calcEFlags() const {
61 void AMDGPU::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
83 RelExpr AMDGPU::getRelExpr(RelType type, const Symbol &s,
105 RelType AMDGPU::getDynRel(RelType type) const {
112 static AMDGPU targe
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUAsmUtils.h13 namespace AMDGPU { namespace in namespace:llvm
40 } // namespace AMDGPU
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
13 /// This file contains definition for AMDGPU ISA disassembler
20 #include "AMDGPU.h"
54 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
55 : AMDGPU::EncValues::SGPR_MAX_SI)
66 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
80 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
270 using namespace llvm::AMDGPU::DPP;
271 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp9 #include "AMDGPU.h"
65 using namespace llvm::AMDGPU;
252 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16);
256 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32);
260 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64);
264 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16);
268 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32);
272 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64);
276 return isRegClass(AMDGPU::VGPR_32RegClassID) ||
277 isRegClass(AMDGPU
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Support/
H A DTargetParser.cpp22 using namespace AMDGPU;
29 AMDGPU::GPUKind Kind;
109 const GPUInfo *getArchEntry(AMDGPU::GPUKind AK, ArrayRef<GPUInfo> Table) {
110 GPUInfo Search = { {""}, {""}, AK, AMDGPU::FEATURE_NONE };
124 StringRef llvm::AMDGPU::getArchNameAMDGCN(GPUKind AK) {
130 StringRef llvm::AMDGPU::getArchNameR600(GPUKind AK) {
136 AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN(StringRef CPU) {
142 return AMDGPU::GPUKind::GK_NONE;
145 AMDGPU
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