Lines Matching refs:AMDGPU
16 #include "AMDGPU.h"
110 case AMDGPU::SI_MASK_BRANCH:
137 if (I->getOpcode() == AMDGPU::S_CBRANCH_VCCNZ ||
138 I->getOpcode() == AMDGPU::S_CBRANCH_VCCZ)
146 I->getOpcode() == AMDGPU::S_WAITCNT)
171 BuildMI(MBB, I, DL, TII->get(AMDGPU::EXP_DONE))
173 .addReg(AMDGPU::VGPR0, RegState::Undef)
174 .addReg(AMDGPU::VGPR0, RegState::Undef)
175 .addReg(AMDGPU::VGPR0, RegState::Undef)
176 .addReg(AMDGPU::VGPR0, RegState::Undef)
180 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ENDPGM)).addImm(0);
226 auto BranchMI = BuildMI(MBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
266 case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR: {
274 Opcode = AMDGPU::V_CMPX_EQ_F32_e64;
278 Opcode = AMDGPU::V_CMPX_LT_F32_e64;
282 Opcode = AMDGPU::V_CMPX_LE_F32_e64;
286 Opcode = AMDGPU::V_CMPX_GT_F32_e64;
290 Opcode = AMDGPU::V_CMPX_GE_F32_e64;
294 Opcode = AMDGPU::V_CMPX_LG_F32_e64;
297 Opcode = AMDGPU::V_CMPX_O_F32_e64;
300 Opcode = AMDGPU::V_CMPX_U_F32_e64;
303 Opcode = AMDGPU::V_CMPX_NLG_F32_e64;
306 Opcode = AMDGPU::V_CMPX_NGE_F32_e64;
309 Opcode = AMDGPU::V_CMPX_NGT_F32_e64;
312 Opcode = AMDGPU::V_CMPX_NLE_F32_e64;
315 Opcode = AMDGPU::V_CMPX_NLT_F32_e64;
318 Opcode = AMDGPU::V_CMPX_NEQ_F32_e64;
326 Opcode = AMDGPU::getVCMPXNoSDstOp(Opcode);
332 Opcode = AMDGPU::getVOPe32(Opcode);
339 I.addReg(AMDGPU::VCC, RegState::Define);
350 case AMDGPU::SI_KILL_I1_TERMINATOR: {
353 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
364 BuildMI(MBB, &MI, DL, TII->get(ST.isWave32() ? AMDGPU::S_MOV_B32
365 : AMDGPU::S_MOV_B64), Exec)
372 unsigned Opcode = KillVal ? AMDGPU::S_ANDN2_B64 : AMDGPU::S_AND_B64;
374 Opcode = KillVal ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_AND_B32;
396 BuildMI(SrcMBB, InsPt, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
419 case AMDGPU::SI_MASK_BRANCH:
423 case AMDGPU::S_BRANCH:
433 case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
434 case AMDGPU::SI_KILL_I1_TERMINATOR: {
459 case AMDGPU::SI_KILL_CLEANUP: