Lines Matching refs:AMDGPU
40 #include "AMDGPU.h"
130 auto DPP32 = AMDGPU::getDPPOp32(Op);
132 auto E32 = AMDGPU::getVOPe32(Op);
133 DPP32 = (E32 == -1)? -1 : AMDGPU::getDPPOp32(E32);
149 case AMDGPU::IMPLICIT_DEF:
151 case AMDGPU::COPY:
152 case AMDGPU::V_MOV_B32_e32: {
166 assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
181 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);
186 const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old);
189 assert(isOfRegClass(CombOldVGPR, AMDGPU::VGPR_32RegClass, *MRI));
203 AMDGPU::OpName::src0_modifiers)) {
204 assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
205 AMDGPU::OpName::src0_modifiers));
209 } else if (AMDGPU::getNamedOperandIdx(DPPOp,
210 AMDGPU::OpName::src0_modifiers) != -1) {
214 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
226 AMDGPU::OpName::src1_modifiers)) {
227 assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
228 AMDGPU::OpName::src1_modifiers));
232 } else if (AMDGPU::getNamedOperandIdx(DPPOp,
233 AMDGPU::OpName::src1_modifiers) != -1) {
237 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
247 if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) {
248 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||
257 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));
258 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));
259 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));
275 case AMDGPU::V_ADD_U32_e32:
276 case AMDGPU::V_ADD_U32_e64:
277 case AMDGPU::V_ADD_I32_e32:
278 case AMDGPU::V_ADD_I32_e64:
279 case AMDGPU::V_OR_B32_e32:
280 case AMDGPU::V_OR_B32_e64:
281 case AMDGPU::V_SUBREV_U32_e32:
282 case AMDGPU::V_SUBREV_U32_e64:
283 case AMDGPU::V_SUBREV_I32_e32:
284 case AMDGPU::V_SUBREV_I32_e64:
285 case AMDGPU::V_MAX_U32_e32:
286 case AMDGPU::V_MAX_U32_e64:
287 case AMDGPU::V_XOR_B32_e32:
288 case AMDGPU::V_XOR_B32_e64:
292 case AMDGPU::V_AND_B32_e32:
293 case AMDGPU::V_AND_B32_e64:
294 case AMDGPU::V_MIN_U32_e32:
295 case AMDGPU::V_MIN_U32_e64:
300 case AMDGPU::V_MIN_I32_e32:
301 case AMDGPU::V_MIN_I32_e64:
306 case AMDGPU::V_MAX_I32_e32:
307 case AMDGPU::V_MAX_I32_e64:
312 case AMDGPU::V_MUL_I32_I24_e32:
313 case AMDGPU::V_MUL_I32_I24_e64:
314 case AMDGPU::V_MUL_U32_U24_e32:
315 case AMDGPU::V_MUL_U32_U24_e64:
330 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
340 if (!isOfRegClass(CombOldVGPR, AMDGPU::VGPR_32RegClass, *MRI)) {
361 assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
364 auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);
377 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);
379 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);
384 auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);
388 auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);
389 auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
446 MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass));
448 TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);
468 if (OrigOp == AMDGPU::REG_SEQUENCE) {
504 if (!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||
505 !hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||
506 !hasNoImmOrEqual(OrigMI, AMDGPU::OpName::clamp, 0) ||
507 !hasNoImmOrEqual(OrigMI, AMDGPU::OpName::omod, 0)) {
516 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);
517 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
592 if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) {
595 } else if (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO) {