Lines Matching refs:AMDGPU
22 #include "AMDGPU.h"
138 using namespace AMDGPU::SDWA;
334 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) {
335 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
338 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) {
339 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) {
369 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
370 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel);
372 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
376 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
377 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel);
378 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
388 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
390 TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused);
393 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) {
399 TII->getNamedImmOperand(MI, AMDGPU::OpName::dst_sel));
400 if (DstSel == AMDGPU::SDWA::SdwaSel::WORD_1 &&
401 getSrcSel() == AMDGPU::SDWA::SdwaSel::WORD_0) {
403 auto DstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
404 AMDGPU::OpName::vdst);
417 if ((MI.getOpcode() == AMDGPU::V_FMAC_F16_sdwa ||
418 MI.getOpcode() == AMDGPU::V_FMAC_F32_sdwa ||
419 MI.getOpcode() == AMDGPU::V_MAC_F16_sdwa ||
420 MI.getOpcode() == AMDGPU::V_MAC_F32_sdwa) &&
461 if ((MI.getOpcode() == AMDGPU::V_FMAC_F16_sdwa ||
462 MI.getOpcode() == AMDGPU::V_FMAC_F32_sdwa ||
463 MI.getOpcode() == AMDGPU::V_MAC_F16_sdwa ||
464 MI.getOpcode() == AMDGPU::V_MAC_F32_sdwa) &&
465 getDstSel() != AMDGPU::SDWA::DWORD) {
470 MachineOperand *Operand = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
475 MachineOperand *DstSel= TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel);
478 MachineOperand *DstUnused= TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused);
511 MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst),
549 case AMDGPU::V_LSHRREV_B32_e32:
550 case AMDGPU::V_ASHRREV_I32_e32:
551 case AMDGPU::V_LSHLREV_B32_e32:
552 case AMDGPU::V_LSHRREV_B32_e64:
553 case AMDGPU::V_ASHRREV_I32_e64:
554 case AMDGPU::V_LSHLREV_B32_e64: {
563 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
571 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
572 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
577 if (Opcode == AMDGPU::V_LSHLREV_B32_e32 ||
578 Opcode == AMDGPU::V_LSHLREV_B32_e64) {
584 Opcode != AMDGPU::V_LSHRREV_B32_e32 &&
585 Opcode != AMDGPU::V_LSHRREV_B32_e64);
590 case AMDGPU::V_LSHRREV_B16_e32:
591 case AMDGPU::V_ASHRREV_I16_e32:
592 case AMDGPU::V_LSHLREV_B16_e32:
593 case AMDGPU::V_LSHRREV_B16_e64:
594 case AMDGPU::V_ASHRREV_I16_e64:
595 case AMDGPU::V_LSHLREV_B16_e64: {
604 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
609 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
610 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
616 if (Opcode == AMDGPU::V_LSHLREV_B16_e32 ||
617 Opcode == AMDGPU::V_LSHLREV_B16_e64) {
622 Opcode != AMDGPU::V_LSHRREV_B16_e32 &&
623 Opcode != AMDGPU::V_LSHRREV_B16_e64);
628 case AMDGPU::V_BFE_I32:
629 case AMDGPU::V_BFE_U32: {
644 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
649 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
673 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
674 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
681 Src0, Dst, SrcSel, false, false, Opcode != AMDGPU::V_BFE_U32);
684 case AMDGPU::V_AND_B32_e32:
685 case AMDGPU::V_AND_B32_e64: {
690 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
691 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
703 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
713 case AMDGPU::V_OR_B32_e32:
714 case AMDGPU::V_OR_B32_e64: {
745 MachineOperand *OrSDWA = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
746 MachineOperand *OrOther = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
750 OrSDWA = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
751 OrOther = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
789 TII->getNamedImmOperand(*SDWAInst, AMDGPU::OpName::dst_sel));;
791 TII->getNamedImmOperand(*OtherInst, AMDGPU::OpName::dst_sel));
831 TII->getNamedImmOperand(*OtherInst, AMDGPU::OpName::dst_unused));
836 MachineOperand *OrDst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
886 assert((Opc == AMDGPU::V_ADD_I32_e64 || Opc == AMDGPU::V_SUB_I32_e64) &&
892 Opc = AMDGPU::getVOPe32(Opc);
894 const MachineOperand *Sdst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst);
904 int SuccOpc = AMDGPU::getVOPe32(MISucc.getOpcode());
906 MachineOperand *CarryIn = TII->getNamedOperand(MISucc, AMDGPU::OpName::src2);
909 MachineOperand *CarryOut = TII->getNamedOperand(MISucc, AMDGPU::OpName::sdst);
916 auto Liveness = MBB.computeRegisterLiveness(TRI, AMDGPU::VCC, MI, 25);
922 if (I->modifiesRegister(AMDGPU::VCC, TRI))
929 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::vdst))
930 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::src0))
931 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::src1))
938 .add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::vdst))
939 .add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::src0))
940 .add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::src1))
954 if (AMDGPU::getSDWAOp(Opc) == -1)
955 Opc = AMDGPU::getVOPe32(Opc);
957 if (AMDGPU::getSDWAOp(Opc) == -1)
960 if (!ST.hasSDWAOmod() && TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
965 const MachineOperand *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst);
966 if (SDst && (SDst->getReg() != AMDGPU::VCC &&
967 SDst->getReg() != AMDGPU::VCC_LO))
972 (TII->hasModifiersSet(MI, AMDGPU::OpName::clamp) ||
973 TII->hasModifiersSet(MI, AMDGPU::OpName::omod)))
976 } else if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst) ||
977 !TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) {
981 if (!ST.hasSDWAMac() && (Opc == AMDGPU::V_FMAC_F16_e32 ||
982 Opc == AMDGPU::V_FMAC_F32_e32 ||
983 Opc == AMDGPU::V_MAC_F16_e32 ||
984 Opc == AMDGPU::V_MAC_F32_e32))
992 if (Opc == AMDGPU::V_CNDMASK_B32_e32)
1009 SDWAOpcode = AMDGPU::getSDWAOp(Opcode);
1011 SDWAOpcode = AMDGPU::getSDWAOp(AMDGPU::getVOPe32(Opcode));
1023 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
1025 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::vdst) != -1);
1027 } else if ((Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst))) {
1029 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1);
1032 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1);
1038 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1041 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src0) != -1 &&
1042 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src0_modifiers) != -1);
1043 if (auto *Mod = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers))
1050 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1053 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1) != -1 &&
1054 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1_modifiers) != -1);
1055 if (auto *Mod = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers))
1062 if (SDWAOpcode == AMDGPU::V_FMAC_F16_sdwa ||
1063 SDWAOpcode == AMDGPU::V_FMAC_F32_sdwa ||
1064 SDWAOpcode == AMDGPU::V_MAC_F16_sdwa ||
1065 SDWAOpcode == AMDGPU::V_MAC_F32_sdwa) {
1067 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
1073 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::clamp) != -1);
1074 MachineOperand *Clamp = TII->getNamedOperand(MI, AMDGPU::OpName::clamp);
1082 if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::omod) != -1) {
1083 MachineOperand *OMod = TII->getNamedOperand(MI, AMDGPU::OpName::omod);
1092 if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::dst_sel) != -1) {
1093 MachineOperand *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel);
1097 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
1102 if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::dst_unused) != -1) {
1103 MachineOperand *DstUnused = TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused);
1107 SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD);
1112 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src0_sel) != -1);
1113 MachineOperand *Src0Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel);
1117 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
1122 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1_sel) != -1);
1123 MachineOperand *Src1Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel);
1127 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD);
1132 auto DstUnused = TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused);
1134 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) {
1140 auto PreserveDstIdx = AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::vdst);
1202 Register VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1204 TII->get(AMDGPU::V_MOV_B32_e32), VGPR);
1238 (PotentialMI->getOpcode() == AMDGPU::V_ADD_I32_e64 ||
1239 PotentialMI->getOpcode() == AMDGPU::V_SUB_I32_e64))