Searched refs:D16 (Results 1 - 11 of 11) sorted by relevance
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 70 case D19: case D18: case D17: case D16:
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| H A D | ARMBaseRegisterInfo.cpp | 168 // Reserve D16-D31 if the subtarget doesn't support them.
170 assert(ARM::D31 == ARM::D16 + 15);
172 Reserved.set(ARM::D16 + i);
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| /freebsd-11.0-release/lib/msun/ld128/ |
| H A D | s_expl.c | 188 * With my coeffs (D11-D16 double):
195 D16 = 4.7628892832607741e-14, /* 0x1.ad00Dfe41feccp-45 */ variable
254 dx * (D14 + dx * (D15 + dx * (D16 +
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.cpp | 93 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 121 case AArch64::D16:
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 128 case AArch64::D16: return AArch64::B16;
168 case AArch64::B16: return AArch64::D16;
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 88 SP::D0, SP::D16, SP::D1, SP::D17,
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 126 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 288 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2957 // Some FPUs only have 16 D registers, so D16-D31 are invalid
2958 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3317 case ARM::Q8: return ARM::D16;
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
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