1//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains small standalone helper functions and enum definitions for 11// the AArch64 target useful for the compiler back-end and the MC libraries. 12// As such, it deliberately does not include references to LLVM core 13// code gen types, passes, etc.. 14// 15//===----------------------------------------------------------------------===// 16 17#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 18#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 19 20// FIXME: Is it easiest to fix this layering violation by moving the .inc 21// #includes from AArch64MCTargetDesc.h to here? 22#include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends. 23#include "llvm/ADT/STLExtras.h" 24#include "llvm/ADT/StringSwitch.h" 25#include "llvm/MC/SubtargetFeature.h" 26#include "llvm/Support/ErrorHandling.h" 27 28namespace llvm { 29 30inline static unsigned getWRegFromXReg(unsigned Reg) { 31 switch (Reg) { 32 case AArch64::X0: return AArch64::W0; 33 case AArch64::X1: return AArch64::W1; 34 case AArch64::X2: return AArch64::W2; 35 case AArch64::X3: return AArch64::W3; 36 case AArch64::X4: return AArch64::W4; 37 case AArch64::X5: return AArch64::W5; 38 case AArch64::X6: return AArch64::W6; 39 case AArch64::X7: return AArch64::W7; 40 case AArch64::X8: return AArch64::W8; 41 case AArch64::X9: return AArch64::W9; 42 case AArch64::X10: return AArch64::W10; 43 case AArch64::X11: return AArch64::W11; 44 case AArch64::X12: return AArch64::W12; 45 case AArch64::X13: return AArch64::W13; 46 case AArch64::X14: return AArch64::W14; 47 case AArch64::X15: return AArch64::W15; 48 case AArch64::X16: return AArch64::W16; 49 case AArch64::X17: return AArch64::W17; 50 case AArch64::X18: return AArch64::W18; 51 case AArch64::X19: return AArch64::W19; 52 case AArch64::X20: return AArch64::W20; 53 case AArch64::X21: return AArch64::W21; 54 case AArch64::X22: return AArch64::W22; 55 case AArch64::X23: return AArch64::W23; 56 case AArch64::X24: return AArch64::W24; 57 case AArch64::X25: return AArch64::W25; 58 case AArch64::X26: return AArch64::W26; 59 case AArch64::X27: return AArch64::W27; 60 case AArch64::X28: return AArch64::W28; 61 case AArch64::FP: return AArch64::W29; 62 case AArch64::LR: return AArch64::W30; 63 case AArch64::SP: return AArch64::WSP; 64 case AArch64::XZR: return AArch64::WZR; 65 } 66 // For anything else, return it unchanged. 67 return Reg; 68} 69 70inline static unsigned getXRegFromWReg(unsigned Reg) { 71 switch (Reg) { 72 case AArch64::W0: return AArch64::X0; 73 case AArch64::W1: return AArch64::X1; 74 case AArch64::W2: return AArch64::X2; 75 case AArch64::W3: return AArch64::X3; 76 case AArch64::W4: return AArch64::X4; 77 case AArch64::W5: return AArch64::X5; 78 case AArch64::W6: return AArch64::X6; 79 case AArch64::W7: return AArch64::X7; 80 case AArch64::W8: return AArch64::X8; 81 case AArch64::W9: return AArch64::X9; 82 case AArch64::W10: return AArch64::X10; 83 case AArch64::W11: return AArch64::X11; 84 case AArch64::W12: return AArch64::X12; 85 case AArch64::W13: return AArch64::X13; 86 case AArch64::W14: return AArch64::X14; 87 case AArch64::W15: return AArch64::X15; 88 case AArch64::W16: return AArch64::X16; 89 case AArch64::W17: return AArch64::X17; 90 case AArch64::W18: return AArch64::X18; 91 case AArch64::W19: return AArch64::X19; 92 case AArch64::W20: return AArch64::X20; 93 case AArch64::W21: return AArch64::X21; 94 case AArch64::W22: return AArch64::X22; 95 case AArch64::W23: return AArch64::X23; 96 case AArch64::W24: return AArch64::X24; 97 case AArch64::W25: return AArch64::X25; 98 case AArch64::W26: return AArch64::X26; 99 case AArch64::W27: return AArch64::X27; 100 case AArch64::W28: return AArch64::X28; 101 case AArch64::W29: return AArch64::FP; 102 case AArch64::W30: return AArch64::LR; 103 case AArch64::WSP: return AArch64::SP; 104 case AArch64::WZR: return AArch64::XZR; 105 } 106 // For anything else, return it unchanged. 107 return Reg; 108} 109 110static inline unsigned getBRegFromDReg(unsigned Reg) { 111 switch (Reg) { 112 case AArch64::D0: return AArch64::B0; 113 case AArch64::D1: return AArch64::B1; 114 case AArch64::D2: return AArch64::B2; 115 case AArch64::D3: return AArch64::B3; 116 case AArch64::D4: return AArch64::B4; 117 case AArch64::D5: return AArch64::B5; 118 case AArch64::D6: return AArch64::B6; 119 case AArch64::D7: return AArch64::B7; 120 case AArch64::D8: return AArch64::B8; 121 case AArch64::D9: return AArch64::B9; 122 case AArch64::D10: return AArch64::B10; 123 case AArch64::D11: return AArch64::B11; 124 case AArch64::D12: return AArch64::B12; 125 case AArch64::D13: return AArch64::B13; 126 case AArch64::D14: return AArch64::B14; 127 case AArch64::D15: return AArch64::B15; 128 case AArch64::D16: return AArch64::B16; 129 case AArch64::D17: return AArch64::B17; 130 case AArch64::D18: return AArch64::B18; 131 case AArch64::D19: return AArch64::B19; 132 case AArch64::D20: return AArch64::B20; 133 case AArch64::D21: return AArch64::B21; 134 case AArch64::D22: return AArch64::B22; 135 case AArch64::D23: return AArch64::B23; 136 case AArch64::D24: return AArch64::B24; 137 case AArch64::D25: return AArch64::B25; 138 case AArch64::D26: return AArch64::B26; 139 case AArch64::D27: return AArch64::B27; 140 case AArch64::D28: return AArch64::B28; 141 case AArch64::D29: return AArch64::B29; 142 case AArch64::D30: return AArch64::B30; 143 case AArch64::D31: return AArch64::B31; 144 } 145 // For anything else, return it unchanged. 146 return Reg; 147} 148 149 150static inline unsigned getDRegFromBReg(unsigned Reg) { 151 switch (Reg) { 152 case AArch64::B0: return AArch64::D0; 153 case AArch64::B1: return AArch64::D1; 154 case AArch64::B2: return AArch64::D2; 155 case AArch64::B3: return AArch64::D3; 156 case AArch64::B4: return AArch64::D4; 157 case AArch64::B5: return AArch64::D5; 158 case AArch64::B6: return AArch64::D6; 159 case AArch64::B7: return AArch64::D7; 160 case AArch64::B8: return AArch64::D8; 161 case AArch64::B9: return AArch64::D9; 162 case AArch64::B10: return AArch64::D10; 163 case AArch64::B11: return AArch64::D11; 164 case AArch64::B12: return AArch64::D12; 165 case AArch64::B13: return AArch64::D13; 166 case AArch64::B14: return AArch64::D14; 167 case AArch64::B15: return AArch64::D15; 168 case AArch64::B16: return AArch64::D16; 169 case AArch64::B17: return AArch64::D17; 170 case AArch64::B18: return AArch64::D18; 171 case AArch64::B19: return AArch64::D19; 172 case AArch64::B20: return AArch64::D20; 173 case AArch64::B21: return AArch64::D21; 174 case AArch64::B22: return AArch64::D22; 175 case AArch64::B23: return AArch64::D23; 176 case AArch64::B24: return AArch64::D24; 177 case AArch64::B25: return AArch64::D25; 178 case AArch64::B26: return AArch64::D26; 179 case AArch64::B27: return AArch64::D27; 180 case AArch64::B28: return AArch64::D28; 181 case AArch64::B29: return AArch64::D29; 182 case AArch64::B30: return AArch64::D30; 183 case AArch64::B31: return AArch64::D31; 184 } 185 // For anything else, return it unchanged. 186 return Reg; 187} 188 189namespace AArch64CC { 190 191// The CondCodes constants map directly to the 4-bit encoding of the condition 192// field for predicated instructions. 193enum CondCode { // Meaning (integer) Meaning (floating-point) 194 EQ = 0x0, // Equal Equal 195 NE = 0x1, // Not equal Not equal, or unordered 196 HS = 0x2, // Unsigned higher or same >, ==, or unordered 197 LO = 0x3, // Unsigned lower Less than 198 MI = 0x4, // Minus, negative Less than 199 PL = 0x5, // Plus, positive or zero >, ==, or unordered 200 VS = 0x6, // Overflow Unordered 201 VC = 0x7, // No overflow Not unordered 202 HI = 0x8, // Unsigned higher Greater than, or unordered 203 LS = 0x9, // Unsigned lower or same Less than or equal 204 GE = 0xa, // Greater than or equal Greater than or equal 205 LT = 0xb, // Less than Less than, or unordered 206 GT = 0xc, // Greater than Greater than 207 LE = 0xd, // Less than or equal <, ==, or unordered 208 AL = 0xe, // Always (unconditional) Always (unconditional) 209 NV = 0xf, // Always (unconditional) Always (unconditional) 210 // Note the NV exists purely to disassemble 0b1111. Execution is "always". 211 Invalid 212}; 213 214inline static const char *getCondCodeName(CondCode Code) { 215 switch (Code) { 216 default: llvm_unreachable("Unknown condition code"); 217 case EQ: return "eq"; 218 case NE: return "ne"; 219 case HS: return "hs"; 220 case LO: return "lo"; 221 case MI: return "mi"; 222 case PL: return "pl"; 223 case VS: return "vs"; 224 case VC: return "vc"; 225 case HI: return "hi"; 226 case LS: return "ls"; 227 case GE: return "ge"; 228 case LT: return "lt"; 229 case GT: return "gt"; 230 case LE: return "le"; 231 case AL: return "al"; 232 case NV: return "nv"; 233 } 234} 235 236inline static CondCode getInvertedCondCode(CondCode Code) { 237 // To reverse a condition it's necessary to only invert the low bit: 238 239 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 240} 241 242/// Given a condition code, return NZCV flags that would satisfy that condition. 243/// The flag bits are in the format expected by the ccmp instructions. 244/// Note that many different flag settings can satisfy a given condition code, 245/// this function just returns one of them. 246inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { 247 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. 248 enum { N = 8, Z = 4, C = 2, V = 1 }; 249 switch (Code) { 250 default: llvm_unreachable("Unknown condition code"); 251 case EQ: return Z; // Z == 1 252 case NE: return 0; // Z == 0 253 case HS: return C; // C == 1 254 case LO: return 0; // C == 0 255 case MI: return N; // N == 1 256 case PL: return 0; // N == 0 257 case VS: return V; // V == 1 258 case VC: return 0; // V == 0 259 case HI: return C; // C == 1 && Z == 0 260 case LS: return 0; // C == 0 || Z == 1 261 case GE: return 0; // N == V 262 case LT: return N; // N != V 263 case GT: return 0; // Z == 0 && N == V 264 case LE: return Z; // Z == 1 || N != V 265 } 266} 267} // end namespace AArch64CC 268 269/// Instances of this class can perform bidirectional mapping from random 270/// identifier strings to operand encodings. For example "MSR" takes a named 271/// system-register which must be encoded somehow and decoded for printing. This 272/// central location means that the information for those transformations is not 273/// duplicated and remains in sync. 274/// 275/// FIXME: currently the algorithm is a completely unoptimised linear 276/// search. Obviously this could be improved, but we would probably want to work 277/// out just how often these instructions are emitted before working on it. It 278/// might even be optimal to just reorder the tables for the common instructions 279/// rather than changing the algorithm. 280struct AArch64NamedImmMapper { 281 struct Mapping { 282 const char *Name; 283 uint32_t Value; 284 // Set of features this mapping is available for 285 // Zero value of FeatureBitSet means the mapping is always available 286 FeatureBitset FeatureBitSet; 287 288 bool isNameEqual(std::string Other, 289 const FeatureBitset& FeatureBits) const { 290 if (FeatureBitSet.any() && 291 (FeatureBitSet & FeatureBits).none()) 292 return false; 293 return Name == Other; 294 } 295 296 bool isValueEqual(uint32_t Other, 297 const FeatureBitset& FeatureBits) const { 298 if (FeatureBitSet.any() && 299 (FeatureBitSet & FeatureBits).none()) 300 return false; 301 return Value == Other; 302 } 303 }; 304 305 template<int N> 306 AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm) 307 : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {} 308 309 // Maps value to string, depending on availability for FeatureBits given 310 StringRef toString(uint32_t Value, const FeatureBitset& FeatureBits, 311 bool &Valid) const; 312 // Maps string to value, depending on availability for FeatureBits given 313 uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits, 314 bool &Valid) const; 315 316 /// Many of the instructions allow an alternative assembly form consisting of 317 /// a simple immediate. Currently the only valid forms are ranges [0, N) where 318 /// N being 0 indicates no immediate syntax-form is allowed. 319 bool validImm(uint32_t Value) const; 320protected: 321 const Mapping *Mappings; 322 size_t NumMappings; 323 uint32_t TooBigImm; 324}; 325 326namespace AArch64AT { 327 enum ATValues { 328 Invalid = -1, // Op0 Op1 CRn CRm Op2 329 S1E1R = 0x43c0, // 01 000 0111 1000 000 330 S1E2R = 0x63c0, // 01 100 0111 1000 000 331 S1E3R = 0x73c0, // 01 110 0111 1000 000 332 S1E1W = 0x43c1, // 01 000 0111 1000 001 333 S1E2W = 0x63c1, // 01 100 0111 1000 001 334 S1E3W = 0x73c1, // 01 110 0111 1000 001 335 S1E0R = 0x43c2, // 01 000 0111 1000 010 336 S1E0W = 0x43c3, // 01 000 0111 1000 011 337 S12E1R = 0x63c4, // 01 100 0111 1000 100 338 S12E1W = 0x63c5, // 01 100 0111 1000 101 339 S12E0R = 0x63c6, // 01 100 0111 1000 110 340 S12E0W = 0x63c7, // 01 100 0111 1000 111 341 S1E1RP = 0x43c8, // 01 000 0111 1001 000 342 S1E1WP = 0x43c9 // 01 000 0111 1001 001 343 }; 344 345 struct ATMapper : AArch64NamedImmMapper { 346 const static Mapping ATMappings[]; 347 348 ATMapper(); 349 }; 350 351} 352namespace AArch64DB { 353 enum DBValues { 354 Invalid = -1, 355 OSHLD = 0x1, 356 OSHST = 0x2, 357 OSH = 0x3, 358 NSHLD = 0x5, 359 NSHST = 0x6, 360 NSH = 0x7, 361 ISHLD = 0x9, 362 ISHST = 0xa, 363 ISH = 0xb, 364 LD = 0xd, 365 ST = 0xe, 366 SY = 0xf 367 }; 368 369 struct DBarrierMapper : AArch64NamedImmMapper { 370 const static Mapping DBarrierMappings[]; 371 372 DBarrierMapper(); 373 }; 374} 375 376namespace AArch64DC { 377 enum DCValues { 378 Invalid = -1, // Op1 CRn CRm Op2 379 ZVA = 0x5ba1, // 01 011 0111 0100 001 380 IVAC = 0x43b1, // 01 000 0111 0110 001 381 ISW = 0x43b2, // 01 000 0111 0110 010 382 CVAC = 0x5bd1, // 01 011 0111 1010 001 383 CSW = 0x43d2, // 01 000 0111 1010 010 384 CVAU = 0x5bd9, // 01 011 0111 1011 001 385 CIVAC = 0x5bf1, // 01 011 0111 1110 001 386 CISW = 0x43f2 // 01 000 0111 1110 010 387 }; 388 389 struct DCMapper : AArch64NamedImmMapper { 390 const static Mapping DCMappings[]; 391 392 DCMapper(); 393 }; 394 395} 396 397namespace AArch64IC { 398 enum ICValues { 399 Invalid = -1, // Op1 CRn CRm Op2 400 IALLUIS = 0x0388, // 000 0111 0001 000 401 IALLU = 0x03a8, // 000 0111 0101 000 402 IVAU = 0x1ba9 // 011 0111 0101 001 403 }; 404 405 406 struct ICMapper : AArch64NamedImmMapper { 407 const static Mapping ICMappings[]; 408 409 ICMapper(); 410 }; 411 412 static inline bool NeedsRegister(ICValues Val) { 413 return Val == IVAU; 414 } 415} 416 417namespace AArch64ISB { 418 enum ISBValues { 419 Invalid = -1, 420 SY = 0xf 421 }; 422 struct ISBMapper : AArch64NamedImmMapper { 423 const static Mapping ISBMappings[]; 424 425 ISBMapper(); 426 }; 427} 428 429namespace AArch64PRFM { 430 enum PRFMValues { 431 Invalid = -1, 432 PLDL1KEEP = 0x00, 433 PLDL1STRM = 0x01, 434 PLDL2KEEP = 0x02, 435 PLDL2STRM = 0x03, 436 PLDL3KEEP = 0x04, 437 PLDL3STRM = 0x05, 438 PLIL1KEEP = 0x08, 439 PLIL1STRM = 0x09, 440 PLIL2KEEP = 0x0a, 441 PLIL2STRM = 0x0b, 442 PLIL3KEEP = 0x0c, 443 PLIL3STRM = 0x0d, 444 PSTL1KEEP = 0x10, 445 PSTL1STRM = 0x11, 446 PSTL2KEEP = 0x12, 447 PSTL2STRM = 0x13, 448 PSTL3KEEP = 0x14, 449 PSTL3STRM = 0x15 450 }; 451 452 struct PRFMMapper : AArch64NamedImmMapper { 453 const static Mapping PRFMMappings[]; 454 455 PRFMMapper(); 456 }; 457} 458 459namespace AArch64PState { 460 enum PStateValues { 461 Invalid = -1, 462 SPSel = 0x05, 463 DAIFSet = 0x1e, 464 DAIFClr = 0x1f, 465 466 // v8.1a "Privileged Access Never" extension-specific PStates 467 PAN = 0x04, 468 469 // v8.2a "User Access Override" extension-specific PStates 470 UAO = 0x03 471 }; 472 473 struct PStateMapper : AArch64NamedImmMapper { 474 const static Mapping PStateMappings[]; 475 476 PStateMapper(); 477 }; 478 479} 480 481namespace AArch64PSBHint { 482 enum PSBHintValues { 483 Invalid = -1, 484 // v8.2a "Statistical Profiling" extension-specific PSB operands 485 CSync = 0x11, // psb csync = hint #0x11 486 }; 487 488 struct PSBHintMapper : AArch64NamedImmMapper { 489 const static Mapping PSBHintMappings[]; 490 491 PSBHintMapper(); 492 }; 493 494} 495 496namespace AArch64SE { 497 enum ShiftExtSpecifiers { 498 Invalid = -1, 499 LSL, 500 MSL, 501 LSR, 502 ASR, 503 ROR, 504 505 UXTB, 506 UXTH, 507 UXTW, 508 UXTX, 509 510 SXTB, 511 SXTH, 512 SXTW, 513 SXTX 514 }; 515} 516 517namespace AArch64Layout { 518 enum VectorLayout { 519 Invalid = -1, 520 VL_8B, 521 VL_4H, 522 VL_2S, 523 VL_1D, 524 525 VL_16B, 526 VL_8H, 527 VL_4S, 528 VL_2D, 529 530 // Bare layout for the 128-bit vector 531 // (only show ".b", ".h", ".s", ".d" without vector number) 532 VL_B, 533 VL_H, 534 VL_S, 535 VL_D 536 }; 537} 538 539inline static const char * 540AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) { 541 switch (Layout) { 542 case AArch64Layout::VL_8B: return ".8b"; 543 case AArch64Layout::VL_4H: return ".4h"; 544 case AArch64Layout::VL_2S: return ".2s"; 545 case AArch64Layout::VL_1D: return ".1d"; 546 case AArch64Layout::VL_16B: return ".16b"; 547 case AArch64Layout::VL_8H: return ".8h"; 548 case AArch64Layout::VL_4S: return ".4s"; 549 case AArch64Layout::VL_2D: return ".2d"; 550 case AArch64Layout::VL_B: return ".b"; 551 case AArch64Layout::VL_H: return ".h"; 552 case AArch64Layout::VL_S: return ".s"; 553 case AArch64Layout::VL_D: return ".d"; 554 default: llvm_unreachable("Unknown Vector Layout"); 555 } 556} 557 558inline static AArch64Layout::VectorLayout 559AArch64StringToVectorLayout(StringRef LayoutStr) { 560 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr) 561 .Case(".8b", AArch64Layout::VL_8B) 562 .Case(".4h", AArch64Layout::VL_4H) 563 .Case(".2s", AArch64Layout::VL_2S) 564 .Case(".1d", AArch64Layout::VL_1D) 565 .Case(".16b", AArch64Layout::VL_16B) 566 .Case(".8h", AArch64Layout::VL_8H) 567 .Case(".4s", AArch64Layout::VL_4S) 568 .Case(".2d", AArch64Layout::VL_2D) 569 .Case(".b", AArch64Layout::VL_B) 570 .Case(".h", AArch64Layout::VL_H) 571 .Case(".s", AArch64Layout::VL_S) 572 .Case(".d", AArch64Layout::VL_D) 573 .Default(AArch64Layout::Invalid); 574} 575 576namespace AArch64SysReg { 577 enum SysRegROValues { 578 MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 579 DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 580 MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 581 OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 582 DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 583 PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 584 PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 585 MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 586 CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 587 CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 588 CTR_EL0 = 0xd801, // 11 011 0000 0000 001 589 MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 590 REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 591 AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 592 DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 593 ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 594 ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 595 ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 596 ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 597 ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 598 ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 599 ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 600 ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 601 ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 602 ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 603 ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 604 ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 605 ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 606 ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 607 ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 608 ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 609 ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 610 ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 611 ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 612 ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 613 ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 614 ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 615 ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 616 ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 617 ID_A64MMFR2_EL1 = 0xc03a, // 11 000 0000 0111 010 618 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 619 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 620 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 621 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 622 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 623 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 624 ISR_EL1 = 0xc608, // 11 000 1100 0001 000 625 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 626 CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 627 ID_MMFR4_EL1 = 0xc016, // 11 000 0000 0010 110 628 629 // Trace registers 630 TRCSTATR = 0x8818, // 10 001 0000 0011 000 631 TRCIDR8 = 0x8806, // 10 001 0000 0000 110 632 TRCIDR9 = 0x880e, // 10 001 0000 0001 110 633 TRCIDR10 = 0x8816, // 10 001 0000 0010 110 634 TRCIDR11 = 0x881e, // 10 001 0000 0011 110 635 TRCIDR12 = 0x8826, // 10 001 0000 0100 110 636 TRCIDR13 = 0x882e, // 10 001 0000 0101 110 637 TRCIDR0 = 0x8847, // 10 001 0000 1000 111 638 TRCIDR1 = 0x884f, // 10 001 0000 1001 111 639 TRCIDR2 = 0x8857, // 10 001 0000 1010 111 640 TRCIDR3 = 0x885f, // 10 001 0000 1011 111 641 TRCIDR4 = 0x8867, // 10 001 0000 1100 111 642 TRCIDR5 = 0x886f, // 10 001 0000 1101 111 643 TRCIDR6 = 0x8877, // 10 001 0000 1110 111 644 TRCIDR7 = 0x887f, // 10 001 0000 1111 111 645 TRCOSLSR = 0x888c, // 10 001 0001 0001 100 646 TRCPDSR = 0x88ac, // 10 001 0001 0101 100 647 TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 648 TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 649 TRCLSR = 0x8bee, // 10 001 0111 1101 110 650 TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 651 TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 652 TRCDEVID = 0x8b97, // 10 001 0111 0010 111 653 TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 654 TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 655 TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 656 TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 657 TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 658 TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 659 TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 660 TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 661 TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 662 TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 663 TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 664 TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 665 TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 666 667 // GICv3 registers 668 ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 669 ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 670 ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 671 ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 672 ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 673 ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 674 ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 675 ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101 676 }; 677 678 enum SysRegWOValues { 679 DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 680 OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 681 PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 682 683 // Trace Registers 684 TRCOSLAR = 0x8884, // 10 001 0001 0000 100 685 TRCLAR = 0x8be6, // 10 001 0111 1100 110 686 687 // GICv3 registers 688 ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 689 ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 690 ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 691 ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 692 ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 693 ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111 694 }; 695 696 enum SysRegValues { 697 Invalid = -1, // Op0 Op1 CRn CRm Op2 698 OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010 699 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010 700 TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000 701 MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000 702 MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010 703 DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000 704 OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010 705 DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000 706 DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100 707 DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100 708 DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100 709 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100 710 DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100 711 DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100 712 DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100 713 DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100 714 DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100 715 DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100 716 DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100 717 DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100 718 DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100 719 DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100 720 DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100 721 DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100 722 DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101 723 DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101 724 DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101 725 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101 726 DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101 727 DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101 728 DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101 729 DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101 730 DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101 731 DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101 732 DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101 733 DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101 734 DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101 735 DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101 736 DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101 737 DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101 738 DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110 739 DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110 740 DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110 741 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110 742 DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110 743 DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110 744 DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110 745 DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110 746 DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110 747 DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110 748 DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110 749 DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110 750 DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110 751 DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110 752 DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110 753 DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110 754 DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111 755 DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111 756 DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111 757 DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111 758 DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111 759 DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111 760 DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111 761 DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111 762 DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111 763 DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111 764 DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111 765 DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111 766 DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111 767 DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111 768 DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111 769 DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111 770 TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000 771 OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100 772 DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100 773 DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110 774 DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110 775 CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000 776 VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000 777 VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101 778 CPACR_EL1 = 0xc082, // 11 000 0001 0000 010 779 SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000 780 SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000 781 SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000 782 ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001 783 ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001 784 ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001 785 HCR_EL2 = 0xe088, // 11 100 0001 0001 000 786 SCR_EL3 = 0xf088, // 11 110 0001 0001 000 787 MDCR_EL2 = 0xe089, // 11 100 0001 0001 001 788 SDER32_EL3 = 0xf089, // 11 110 0001 0001 001 789 CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010 790 CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010 791 HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011 792 HACR_EL2 = 0xe08f, // 11 100 0001 0001 111 793 MDCR_EL3 = 0xf099, // 11 110 0001 0011 001 794 TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000 795 TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000 796 TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000 797 TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001 798 TCR_EL1 = 0xc102, // 11 000 0010 0000 010 799 TCR_EL2 = 0xe102, // 11 100 0010 0000 010 800 TCR_EL3 = 0xf102, // 11 110 0010 0000 010 801 VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000 802 VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010 803 DACR32_EL2 = 0xe180, // 11 100 0011 0000 000 804 SPSR_EL1 = 0xc200, // 11 000 0100 0000 000 805 SPSR_EL2 = 0xe200, // 11 100 0100 0000 000 806 SPSR_EL3 = 0xf200, // 11 110 0100 0000 000 807 ELR_EL1 = 0xc201, // 11 000 0100 0000 001 808 ELR_EL2 = 0xe201, // 11 100 0100 0000 001 809 ELR_EL3 = 0xf201, // 11 110 0100 0000 001 810 SP_EL0 = 0xc208, // 11 000 0100 0001 000 811 SP_EL1 = 0xe208, // 11 100 0100 0001 000 812 SP_EL2 = 0xf208, // 11 110 0100 0001 000 813 SPSel = 0xc210, // 11 000 0100 0010 000 814 NZCV = 0xda10, // 11 011 0100 0010 000 815 DAIF = 0xda11, // 11 011 0100 0010 001 816 CurrentEL = 0xc212, // 11 000 0100 0010 010 817 SPSR_irq = 0xe218, // 11 100 0100 0011 000 818 SPSR_abt = 0xe219, // 11 100 0100 0011 001 819 SPSR_und = 0xe21a, // 11 100 0100 0011 010 820 SPSR_fiq = 0xe21b, // 11 100 0100 0011 011 821 FPCR = 0xda20, // 11 011 0100 0100 000 822 FPSR = 0xda21, // 11 011 0100 0100 001 823 DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000 824 DLR_EL0 = 0xda29, // 11 011 0100 0101 001 825 IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001 826 AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000 827 AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000 828 AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000 829 AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001 830 AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001 831 AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001 832 ESR_EL1 = 0xc290, // 11 000 0101 0010 000 833 ESR_EL2 = 0xe290, // 11 100 0101 0010 000 834 ESR_EL3 = 0xf290, // 11 110 0101 0010 000 835 FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000 836 FAR_EL1 = 0xc300, // 11 000 0110 0000 000 837 FAR_EL2 = 0xe300, // 11 100 0110 0000 000 838 FAR_EL3 = 0xf300, // 11 110 0110 0000 000 839 HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100 840 PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000 841 PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000 842 PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001 843 PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010 844 PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011 845 PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101 846 PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000 847 PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001 848 PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010 849 PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000 850 PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001 851 PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010 852 PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011 853 MAIR_EL1 = 0xc510, // 11 000 1010 0010 000 854 MAIR_EL2 = 0xe510, // 11 100 1010 0010 000 855 MAIR_EL3 = 0xf510, // 11 110 1010 0010 000 856 AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000 857 AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000 858 AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000 859 VBAR_EL1 = 0xc600, // 11 000 1100 0000 000 860 VBAR_EL2 = 0xe600, // 11 100 1100 0000 000 861 VBAR_EL3 = 0xf600, // 11 110 1100 0000 000 862 RMR_EL1 = 0xc602, // 11 000 1100 0000 010 863 RMR_EL2 = 0xe602, // 11 100 1100 0000 010 864 RMR_EL3 = 0xf602, // 11 110 1100 0000 010 865 CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001 866 TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010 867 TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010 868 TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010 869 TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011 870 TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100 871 CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000 872 CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011 873 CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000 874 CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000 875 CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000 876 CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000 877 CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000 878 CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001 879 CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001 880 CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001 881 CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010 882 CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010 883 CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010 884 CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000 885 CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001 886 CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010 887 PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000 888 PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001 889 PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010 890 PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011 891 PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100 892 PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101 893 PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110 894 PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111 895 PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000 896 PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001 897 PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010 898 PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011 899 PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100 900 PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101 901 PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110 902 PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111 903 PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000 904 PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001 905 PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010 906 PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011 907 PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100 908 PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101 909 PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110 910 PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111 911 PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000 912 PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001 913 PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010 914 PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011 915 PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100 916 PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101 917 PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110 918 PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111 919 PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000 920 PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001 921 PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010 922 PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011 923 PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100 924 PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101 925 PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110 926 PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111 927 PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000 928 PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001 929 PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010 930 PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011 931 PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100 932 PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101 933 PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110 934 PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111 935 PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000 936 PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001 937 PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010 938 PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011 939 PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100 940 PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101 941 PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110 942 PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111 943 PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000 944 PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001 945 PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010 946 PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011 947 PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100 948 PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101 949 PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110 950 951 // Trace registers 952 TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000 953 TRCPROCSELR = 0x8810, // 10 001 0000 0010 000 954 TRCCONFIGR = 0x8820, // 10 001 0000 0100 000 955 TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000 956 TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000 957 TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000 958 TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000 959 TRCTSCTLR = 0x8860, // 10 001 0000 1100 000 960 TRCSYNCPR = 0x8868, // 10 001 0000 1101 000 961 TRCCCCTLR = 0x8870, // 10 001 0000 1110 000 962 TRCBBCTLR = 0x8878, // 10 001 0000 1111 000 963 TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001 964 TRCQCTLR = 0x8809, // 10 001 0000 0001 001 965 TRCVICTLR = 0x8802, // 10 001 0000 0000 010 966 TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010 967 TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010 968 TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010 969 TRCVDCTLR = 0x8842, // 10 001 0000 1000 010 970 TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010 971 TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010 972 TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100 973 TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100 974 TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100 975 TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100 976 TRCSEQSTR = 0x883c, // 10 001 0000 0111 100 977 TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100 978 TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101 979 TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101 980 TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101 981 TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101 982 TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101 983 TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101 984 TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101 985 TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101 986 TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101 987 TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101 988 TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101 989 TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101 990 TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111 991 TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111 992 TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111 993 TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111 994 TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111 995 TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111 996 TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111 997 TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111 998 TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000 999 TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000 1000 TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000 1001 TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000 1002 TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000 1003 TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000 1004 TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000 1005 TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000 1006 TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000 1007 TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000 1008 TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000 1009 TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000 1010 TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000 1011 TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000 1012 TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001 1013 TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001 1014 TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001 1015 TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001 1016 TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001 1017 TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001 1018 TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001 1019 TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001 1020 TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001 1021 TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001 1022 TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001 1023 TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001 1024 TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001 1025 TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001 1026 TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001 1027 TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001 1028 TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010 1029 TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010 1030 TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010 1031 TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010 1032 TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010 1033 TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010 1034 TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010 1035 TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010 1036 TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010 1037 TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010 1038 TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010 1039 TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010 1040 TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010 1041 TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010 1042 TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010 1043 TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010 1044 TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011 1045 TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011 1046 TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011 1047 TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011 1048 TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011 1049 TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011 1050 TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011 1051 TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011 1052 TRCPDCR = 0x88a4, // 10 001 0001 0100 100 1053 TRCACVR0 = 0x8900, // 10 001 0010 0000 000 1054 TRCACVR1 = 0x8910, // 10 001 0010 0010 000 1055 TRCACVR2 = 0x8920, // 10 001 0010 0100 000 1056 TRCACVR3 = 0x8930, // 10 001 0010 0110 000 1057 TRCACVR4 = 0x8940, // 10 001 0010 1000 000 1058 TRCACVR5 = 0x8950, // 10 001 0010 1010 000 1059 TRCACVR6 = 0x8960, // 10 001 0010 1100 000 1060 TRCACVR7 = 0x8970, // 10 001 0010 1110 000 1061 TRCACVR8 = 0x8901, // 10 001 0010 0000 001 1062 TRCACVR9 = 0x8911, // 10 001 0010 0010 001 1063 TRCACVR10 = 0x8921, // 10 001 0010 0100 001 1064 TRCACVR11 = 0x8931, // 10 001 0010 0110 001 1065 TRCACVR12 = 0x8941, // 10 001 0010 1000 001 1066 TRCACVR13 = 0x8951, // 10 001 0010 1010 001 1067 TRCACVR14 = 0x8961, // 10 001 0010 1100 001 1068 TRCACVR15 = 0x8971, // 10 001 0010 1110 001 1069 TRCACATR0 = 0x8902, // 10 001 0010 0000 010 1070 TRCACATR1 = 0x8912, // 10 001 0010 0010 010 1071 TRCACATR2 = 0x8922, // 10 001 0010 0100 010 1072 TRCACATR3 = 0x8932, // 10 001 0010 0110 010 1073 TRCACATR4 = 0x8942, // 10 001 0010 1000 010 1074 TRCACATR5 = 0x8952, // 10 001 0010 1010 010 1075 TRCACATR6 = 0x8962, // 10 001 0010 1100 010 1076 TRCACATR7 = 0x8972, // 10 001 0010 1110 010 1077 TRCACATR8 = 0x8903, // 10 001 0010 0000 011 1078 TRCACATR9 = 0x8913, // 10 001 0010 0010 011 1079 TRCACATR10 = 0x8923, // 10 001 0010 0100 011 1080 TRCACATR11 = 0x8933, // 10 001 0010 0110 011 1081 TRCACATR12 = 0x8943, // 10 001 0010 1000 011 1082 TRCACATR13 = 0x8953, // 10 001 0010 1010 011 1083 TRCACATR14 = 0x8963, // 10 001 0010 1100 011 1084 TRCACATR15 = 0x8973, // 10 001 0010 1110 011 1085 TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100 1086 TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100 1087 TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100 1088 TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100 1089 TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101 1090 TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101 1091 TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101 1092 TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101 1093 TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110 1094 TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110 1095 TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110 1096 TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110 1097 TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111 1098 TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111 1099 TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111 1100 TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111 1101 TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000 1102 TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000 1103 TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000 1104 TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000 1105 TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000 1106 TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000 1107 TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000 1108 TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000 1109 TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001 1110 TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001 1111 TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001 1112 TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001 1113 TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001 1114 TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001 1115 TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001 1116 TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001 1117 TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010 1118 TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010 1119 TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010 1120 TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010 1121 TRCITCTRL = 0x8b84, // 10 001 0111 0000 100 1122 TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110 1123 TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110 1124 1125 // GICv3 registers 1126 ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011 1127 ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011 1128 ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000 1129 ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100 1130 ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100 1131 ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101 1132 ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101 1133 ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101 1134 ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110 1135 ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111 1136 ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111 1137 ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000 1138 ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100 1139 ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101 1140 ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110 1141 ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111 1142 ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000 1143 ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001 1144 ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010 1145 ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011 1146 ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000 1147 ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001 1148 ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010 1149 ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011 1150 ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000 1151 ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001 1152 ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010 1153 ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011 1154 ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000 1155 ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010 1156 ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111 1157 ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100 1158 ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000 1159 ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001 1160 ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010 1161 ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011 1162 ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100 1163 ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101 1164 ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110 1165 ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111 1166 ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000 1167 ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001 1168 ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010 1169 ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011 1170 ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100 1171 ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101 1172 ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110 1173 ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111 1174 1175 // v8.1a "Privileged Access Never" extension-specific system registers 1176 PAN = 0xc213, // 11 000 0100 0010 011 1177 1178 // v8.1a "Limited Ordering Regions" extension-specific system registers 1179 LORSA_EL1 = 0xc520, // 11 000 1010 0100 000 1180 LOREA_EL1 = 0xc521, // 11 000 1010 0100 001 1181 LORN_EL1 = 0xc522, // 11 000 1010 0100 010 1182 LORC_EL1 = 0xc523, // 11 000 1010 0100 011 1183 LORID_EL1 = 0xc527, // 11 000 1010 0100 111 1184 1185 // v8.1a "Virtualization host extensions" system registers 1186 TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001 1187 CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001 1188 CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000 1189 CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010 1190 CNTHV_CTL_EL2 = 0xe719, // 11 100 1110 0011 001 1191 SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000 1192 CPACR_EL12 = 0xe882, // 11 101 0001 0000 010 1193 TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000 1194 TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001 1195 TCR_EL12 = 0xe902, // 11 101 0010 0000 010 1196 AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000 1197 AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001 1198 ESR_EL12 = 0xea90, // 11 101 0101 0010 000 1199 FAR_EL12 = 0xeb00, // 11 101 0110 0000 000 1200 MAIR_EL12 = 0xed10, // 11 101 1010 0010 000 1201 AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000 1202 VBAR_EL12 = 0xee00, // 11 101 1100 0000 000 1203 CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001 1204 CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000 1205 CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000 1206 CNTP_CTL_EL02 = 0xef11, // 11 101 1110 0010 001 1207 CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010 1208 CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000 1209 CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001 1210 CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010 1211 SPSR_EL12 = 0xea00, // 11 101 0100 0000 000 1212 ELR_EL12 = 0xea01, // 11 101 0100 0000 001 1213 1214 // v8.2a registers 1215 UAO = 0xc214, // 11 000 0100 0010 100 1216 1217 // v8.2a "Statistical Profiling extension" registers 1218 PMBLIMITR_EL1 = 0xc4d0, // 11 000 1001 1010 000 1219 PMBPTR_EL1 = 0xc4d1, // 11 000 1001 1010 001 1220 PMBSR_EL1 = 0xc4d3, // 11 000 1001 1010 011 1221 PMBIDR_EL1 = 0xc4d7, // 11 000 1001 1010 111 1222 PMSCR_EL2 = 0xe4c8, // 11 100 1001 1001 000 1223 PMSCR_EL12 = 0xecc8, // 11 101 1001 1001 000 1224 PMSCR_EL1 = 0xc4c8, // 11 000 1001 1001 000 1225 PMSICR_EL1 = 0xc4ca, // 11 000 1001 1001 010 1226 PMSIRR_EL1 = 0xc4cb, // 11 000 1001 1001 011 1227 PMSFCR_EL1 = 0xc4cc, // 11 000 1001 1001 100 1228 PMSEVFR_EL1 = 0xc4cd, // 11 000 1001 1001 101 1229 PMSLATFR_EL1 = 0xc4ce, // 11 000 1001 1001 110 1230 PMSIDR_EL1 = 0xc4cf, // 11 000 1001 1001 111 1231 1232 // Cyclone specific system registers 1233 CPM_IOACC_CTL_EL3 = 0xff90, 1234 }; 1235 1236 // Note that these do not inherit from AArch64NamedImmMapper. This class is 1237 // sufficiently different in its behaviour that I don't believe it's worth 1238 // burdening the common AArch64NamedImmMapper with abstractions only needed in 1239 // this one case. 1240 struct SysRegMapper { 1241 static const AArch64NamedImmMapper::Mapping SysRegMappings[]; 1242 1243 const AArch64NamedImmMapper::Mapping *InstMappings; 1244 size_t NumInstMappings; 1245 1246 SysRegMapper() { } 1247 uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits, 1248 bool &Valid) const; 1249 std::string toString(uint32_t Bits, const FeatureBitset& FeatureBits) const; 1250 }; 1251 1252 struct MSRMapper : SysRegMapper { 1253 static const AArch64NamedImmMapper::Mapping MSRMappings[]; 1254 MSRMapper(); 1255 }; 1256 1257 struct MRSMapper : SysRegMapper { 1258 static const AArch64NamedImmMapper::Mapping MRSMappings[]; 1259 MRSMapper(); 1260 }; 1261 1262 uint32_t ParseGenericRegister(StringRef Name, bool &Valid); 1263} 1264 1265namespace AArch64TLBI { 1266 enum TLBIValues { 1267 Invalid = -1, // Op0 Op1 CRn CRm Op2 1268 IPAS2E1IS = 0x6401, // 01 100 1000 0000 001 1269 IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101 1270 VMALLE1IS = 0x4418, // 01 000 1000 0011 000 1271 ALLE2IS = 0x6418, // 01 100 1000 0011 000 1272 ALLE3IS = 0x7418, // 01 110 1000 0011 000 1273 VAE1IS = 0x4419, // 01 000 1000 0011 001 1274 VAE2IS = 0x6419, // 01 100 1000 0011 001 1275 VAE3IS = 0x7419, // 01 110 1000 0011 001 1276 ASIDE1IS = 0x441a, // 01 000 1000 0011 010 1277 VAAE1IS = 0x441b, // 01 000 1000 0011 011 1278 ALLE1IS = 0x641c, // 01 100 1000 0011 100 1279 VALE1IS = 0x441d, // 01 000 1000 0011 101 1280 VALE2IS = 0x641d, // 01 100 1000 0011 101 1281 VALE3IS = 0x741d, // 01 110 1000 0011 101 1282 VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110 1283 VAALE1IS = 0x441f, // 01 000 1000 0011 111 1284 IPAS2E1 = 0x6421, // 01 100 1000 0100 001 1285 IPAS2LE1 = 0x6425, // 01 100 1000 0100 101 1286 VMALLE1 = 0x4438, // 01 000 1000 0111 000 1287 ALLE2 = 0x6438, // 01 100 1000 0111 000 1288 ALLE3 = 0x7438, // 01 110 1000 0111 000 1289 VAE1 = 0x4439, // 01 000 1000 0111 001 1290 VAE2 = 0x6439, // 01 100 1000 0111 001 1291 VAE3 = 0x7439, // 01 110 1000 0111 001 1292 ASIDE1 = 0x443a, // 01 000 1000 0111 010 1293 VAAE1 = 0x443b, // 01 000 1000 0111 011 1294 ALLE1 = 0x643c, // 01 100 1000 0111 100 1295 VALE1 = 0x443d, // 01 000 1000 0111 101 1296 VALE2 = 0x643d, // 01 100 1000 0111 101 1297 VALE3 = 0x743d, // 01 110 1000 0111 101 1298 VMALLS12E1 = 0x643e, // 01 100 1000 0111 110 1299 VAALE1 = 0x443f // 01 000 1000 0111 111 1300 }; 1301 1302 struct TLBIMapper : AArch64NamedImmMapper { 1303 const static Mapping TLBIMappings[]; 1304 1305 TLBIMapper(); 1306 }; 1307 1308 static inline bool NeedsRegister(TLBIValues Val) { 1309 switch (Val) { 1310 case VMALLE1IS: 1311 case ALLE2IS: 1312 case ALLE3IS: 1313 case ALLE1IS: 1314 case VMALLS12E1IS: 1315 case VMALLE1: 1316 case ALLE2: 1317 case ALLE3: 1318 case ALLE1: 1319 case VMALLS12E1: 1320 return false; 1321 default: 1322 return true; 1323 } 1324 } 1325} 1326 1327namespace AArch64II { 1328 /// Target Operand Flag enum. 1329 enum TOF { 1330 //===------------------------------------------------------------------===// 1331 // AArch64 Specific MachineOperand flags. 1332 1333 MO_NO_FLAG, 1334 1335 MO_FRAGMENT = 0xf, 1336 1337 /// MO_PAGE - A symbol operand with this flag represents the pc-relative 1338 /// offset of the 4K page containing the symbol. This is used with the 1339 /// ADRP instruction. 1340 MO_PAGE = 1, 1341 1342 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of 1343 /// that symbol within a 4K page. This offset is added to the page address 1344 /// to produce the complete address. 1345 MO_PAGEOFF = 2, 1346 1347 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high 1348 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction 1349 MO_G3 = 3, 1350 1351 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits 1352 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction 1353 MO_G2 = 4, 1354 1355 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits 1356 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction 1357 MO_G1 = 5, 1358 1359 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits 1360 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction 1361 MO_G0 = 6, 1362 1363 /// MO_HI12 - This flag indicates that a symbol operand represents the bits 1364 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- 1365 /// by-12-bits instruction. 1366 MO_HI12 = 7, 1367 1368 /// MO_GOT - This flag indicates that a symbol operand represents the 1369 /// address of the GOT entry for the symbol, rather than the address of 1370 /// the symbol itself. 1371 MO_GOT = 0x10, 1372 1373 /// MO_NC - Indicates whether the linker is expected to check the symbol 1374 /// reference for overflow. For example in an ADRP/ADD pair of relocations 1375 /// the ADRP usually does check, but not the ADD. 1376 MO_NC = 0x20, 1377 1378 /// MO_TLS - Indicates that the operand being accessed is some kind of 1379 /// thread-local symbol. On Darwin, only one type of thread-local access 1380 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the 1381 /// referee will affect interpretation. 1382 MO_TLS = 0x40, 1383 1384 /// MO_CONSTPOOL - This flag indicates that a symbol operand represents 1385 /// the address of a constant pool entry for the symbol, rather than the 1386 /// address of the symbol itself. 1387 MO_CONSTPOOL = 0x80 1388 }; 1389} // end namespace AArch64II 1390 1391} // end namespace llvm 1392 1393#endif 1394