/freebsd-11.0-release/sys/arm/amlogic/aml8726/ |
H A D | aml8726_pic.c | 111 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro 126 CSR_WRITE_4(aml8726_pic_sc, AML_PIC_STAT_CLR_REG(nb), AML_PIC_BIT(nb)); 167 CSR_WRITE_4(sc, AML_PIC_0_MASK_REG + i * 16, 0); 168 CSR_WRITE_4(sc, AML_PIC_0_STAT_CLR_REG + i * 16, ~0u); 169 CSR_WRITE_4(sc, AML_PIC_0_FIRQ_SEL + i * 16, 0); 255 CSR_WRITE_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb), mask); 274 CSR_WRITE_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb), mask);
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H A D | aml8726_rtc.c | 125 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro 136 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & 152 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | 164 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | 171 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & 182 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | 185 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & 200 CSR_WRITE_4(sc, AML_RTC_0_REG, 280 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & 301 CSR_WRITE_4(s [all...] |
H A D | aml8726_usb_phy-m3.c | 103 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro 258 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); 267 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); 274 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); 281 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); 288 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); 295 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); 302 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); 309 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); 320 CSR_WRITE_4(s [all...] |
H A D | aml8726_timer.c | 130 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro 152 CSR_WRITE_4(sc, AML_TIMER_A_REG, sc->period_ticks); 153 CSR_WRITE_4(sc, AML_TIMER_MUX_REG, 196 CSR_WRITE_4(sc, AML_TIMER_A_REG, ticks); 197 CSR_WRITE_4(sc, AML_TIMER_MUX_REG, 214 CSR_WRITE_4(sc, AML_TIMER_MUX_REG, 257 CSR_WRITE_4(sc, AML_TIMER_MUX_REG, 264 CSR_WRITE_4(sc, AML_TIMER_E_REG, 0); 266 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
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H A D | aml8726_wdt.c | 101 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro 124 CSR_WRITE_4(sc, AML_WDT_RESET_REG, 0); 125 CSR_WRITE_4(sc, AML_WDT_CTRL_REG, wcr); 129 CSR_WRITE_4(sc, AML_WDT_CTRL_REG, 150 CSR_WRITE_4(sc, AML_WDT_CTRL_REG, 241 CSR_WRITE_4(sc, AML_WDT_CTRL_REG, 301 CSR_WRITE_4(aml8726_wdt_sc, AML_WDT_RESET_REG, 0); 302 CSR_WRITE_4(aml8726_wdt_sc, AML_WDT_CTRL_REG,
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H A D | aml8726_sdxc-m8.c | 153 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro 207 CSR_WRITE_4(sc, AML_SDXC_SOFT_RESET_REG, AML_SDXC_SOFT_RESET); 239 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); 246 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); 250 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); 284 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); 291 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); 309 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); 427 CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, ier); 429 CSR_WRITE_4(s [all...] |
H A D | aml8726_gpio.c | 87 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[reg], 0, (val)) macro 248 CSR_WRITE_4(sc, AML_GPIO_OE_N_REG, 252 CSR_WRITE_4(sc, AML_GPIO_OE_N_REG, 281 CSR_WRITE_4(sc, AML_GPIO_OUT_REG, 324 CSR_WRITE_4(sc, AML_GPIO_OUT_REG,
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/freebsd-11.0-release/sys/dev/et/ |
H A D | if_et.c | 314 CSR_WRITE_4(sc, ET_PM, pmcfg); 426 CSR_WRITE_4(sc, ET_MII_CMD, 0); 430 CSR_WRITE_4(sc, ET_MII_ADDR, val); 433 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 457 CSR_WRITE_4(sc, ET_MII_CMD, 0); 470 CSR_WRITE_4(sc, ET_MII_CMD, 0); 474 CSR_WRITE_4(sc, ET_MII_ADDR, val); 477 CSR_WRITE_4(sc, ET_MII_CTRL, 497 CSR_WRITE_4(sc, ET_MII_CMD, 0); 579 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/lge/ |
H A D | if_lge.c | 197 CSR_WRITE_4(sc, reg, \ 201 CSR_WRITE_4(sc, reg, \ 205 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 222 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 288 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 312 CSR_WRITE_4(sc, LGE_GMIICTL, 380 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 383 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 384 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/sis/ |
H A D | if_sis.c | 118 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) macro 195 CSR_WRITE_4(sc, reg, \ 199 CSR_WRITE_4(sc, reg, \ 203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 206 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 253 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 418 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 419 CSR_WRITE_4(sc, SIS_CSR, 0); 421 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 423 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/wb/ |
H A D | if_wb.c | 236 CSR_WRITE_4(sc, reg, \ 240 CSR_WRITE_4(sc, reg, \ 244 CSR_WRITE_4(sc, WB_SIO, \ 248 CSR_WRITE_4(sc, WB_SIO, \ 293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 300 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 315 CSR_WRITE_4(sc, WB_SIO, 0); 372 CSR_WRITE_4(sc, WB_SIO, val); 429 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 430 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/alc/ |
H A D | if_alc.c | 290 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 317 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 354 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 380 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 438 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 470 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 476 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 500 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 506 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 707 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/bfe/ |
H A D | if_bfe.c | 682 CSR_WRITE_4(sc, BFE_RXCONF, flow); 689 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 692 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 753 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 868 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 872 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 884 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 911 CSR_WRITE_4(sc, BFE_IMASK, 0); 914 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 917 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/nge/ |
H A D | if_nge.c | 247 CSR_WRITE_4(sc, reg, \ 251 CSR_WRITE_4(sc, reg, \ 255 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 258 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 290 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 407 CSR_WRITE_4(sc, NGE_MEAR, val); 498 CSR_WRITE_4(sc, reg, data); 602 CSR_WRITE_4(sc, NGE_CFG, reg); 607 CSR_WRITE_4(sc, NGE_CSR, reg); 631 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/tx/ |
H A D | if_tx.c | 355 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 360 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 367 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F); 713 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED); 872 CSR_WRITE_4(sc, INTSTAT, status); 884 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED); 953 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO); 1049 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1108 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1124 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/sge/ |
H A D | if_sge.c | 182 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val) macro 217 CSR_WRITE_4(sc, ROMInterface, 338 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) | 362 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) | 436 CSR_WRITE_4(sc, StationControl, ctl); 438 CSR_WRITE_4(sc, RGMIIDelay, 0x0441); 439 CSR_WRITE_4(sc, RGMIIDelay, 0x0440); 480 CSR_WRITE_4(sc, RxHashTable, hashes[0]); 481 CSR_WRITE_4(sc, RxHashTable2, hashes[1]); 507 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/dc/ |
H A D | dcphy.c | 74 CSR_WRITE_4(sc, reg, \ 78 CSR_WRITE_4(sc, reg, \ 157 CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0); 158 CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0); 226 CSR_WRITE_4(dc_sc, DC_NETCFG, mode); 243 CSR_WRITE_4(dc_sc, DC_NETCFG, mode); 387 CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF); 389 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFF);
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H A D | if_dc.c | 363 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 366 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 389 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 431 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 449 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 469 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 521 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 545 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 548 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 567 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/ipw/ |
H A D | if_ipwreg.h | 340 #define CSR_WRITE_4(sc, reg, val) \ macro 351 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \ 355 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \ 359 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 364 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 369 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 370 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 374 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
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/freebsd-11.0-release/sys/dev/jme/ |
H A D | if_jme.c | 227 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 258 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 371 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 546 CSR_WRITE_4(sc, JME_PAR0, 548 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 616 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); 617 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); 618 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); 619 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); 1593 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/bge/ |
H A D | if_bge.c | 657 CSR_WRITE_4(sc, off, val); 666 CSR_WRITE_4(sc, off, val); 1008 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1019 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1021 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1022 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1042 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1045 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1092 CSR_WRITE_4(sc, BGE_EE_ADDR, 1097 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/altera/atse/ |
H A D | if_atse.c | 321 #define CSR_WRITE_4(sc, reg, val) \ macro 508 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 563 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 568 CSR_WRITE_4(sc, MHASH_START + i, 0x1); 592 CSR_WRITE_4(sc, MHASH_START + i, 766 CSR_WRITE_4(sc, BASE_CFG_MAC_0, v0); 767 CSR_WRITE_4(sc, BASE_CFG_MAC_1, v1); 770 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_0_0, v0); 771 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_0_1, v1); 774 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/my/ |
H A D | if_my.c | 142 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 143 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 186 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 190 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 204 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 207 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 239 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 257 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 284 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/ti/ |
H A D | if_ti.c | 437 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 467 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 494 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 562 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 631 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 687 CSR_WRITE_4(sc, TI_WINBASE, origwin); 724 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 775 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 844 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 865 CSR_WRITE_4(s [all...] |
/freebsd-11.0-release/sys/dev/msk/ |
H A D | if_msk.c | 552 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 634 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 636 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 641 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 1256 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1301 CSR_WRITE_4(sc, B2_GP_IO, val); 1359 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1368 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1422 CSR_WRITE_4(s [all...] |