dev/lge/if_lge.c

197 	CSR_WRITE_4(sc, reg,				\
201 	CSR_WRITE_4(sc, reg,				\
205 	CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
208 	CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
222 	CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
288 	CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
312 	CSR_WRITE_4(sc, LGE_GMIICTL,
380 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
383 		CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
384 		CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
389 	CSR_WRITE_4(sc, LGE_MAR0, 0);
390 	CSR_WRITE_4(sc, LGE_MAR1, 0);
406 	CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
407 	CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
667 	CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
748 	CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
1038 	CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1040 	CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1112 	CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1164 	CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1265 	CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0]));
1266 	CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4]));
1282 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1289 		CSR_WRITE_4(sc, LGE_MODE1,
1292 		CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1299 		CSR_WRITE_4(sc, LGE_MODE1,
1302 		CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1306 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1309 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1312 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1315 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1316 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1319 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1322 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1325 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1330 	CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1341 	CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1349 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1352 	CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1353 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1355 	CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1356 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1361 	CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1458 				CSR_WRITE_4(sc, LGE_MODE1,
1464 				CSR_WRITE_4(sc, LGE_MODE1,
1534 	CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1537 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);