dev/msk/if_msk.c

552 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
634 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
636 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
639 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
641 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
1256 		CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1301 			CSR_WRITE_4(sc, B2_GP_IO, val);
1359 			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1368 			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1422 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
1423 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
1424 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1427 			CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL),
1437 		CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
1445 	CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1495 	CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1497 	CSR_WRITE_4(sc, B0_IMSK, 0);
1528 	CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
1529 	CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
1532 	CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
1533 	CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
1551 		CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
1556 	CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
1559 	CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
2094 	CSR_WRITE_4(sc, B0_IMSK, 0);
2096 	CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
3039 	CSR_WRITE_4(sc, B0_IMSK, 0);
3041 	CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
3426 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3430 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3469 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3475 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3480 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3552 				CSR_WRITE_4(sc, B0_HWE_IMSK,
3706 		CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3730 		CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3736 		CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3744 		CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3747 	CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3770 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3775 			CSR_WRITE_4(sc,
3779 			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3782 			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3834 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
3835 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
3836 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
3839 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
3897 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3898 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3903 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
3910 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0);
3913 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3929 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3930 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3931 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3951 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
3970 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3971 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3972 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3988 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
3994 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3995 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3996 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
4001                 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
4015 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
4036 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
4049 	CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask);
4052 		CSR_WRITE_4(sc, B2_IRQM_INI,
4054 		CSR_WRITE_4(sc, B2_IRQM_VAL,
4059 	CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4061 	CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4085 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
4087 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
4089 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
4091 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
4100 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
4101 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
4109 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
4111 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
4113 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
4115 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
4129 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4131 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4134 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
4136 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
4142 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4174 	CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4176 	CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4189 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4193 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4214 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4218 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
4225 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
4227 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
4250 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
4253 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
4258 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);