dev/sge/if_sge.c

182 #define	CSR_WRITE_4(sc, reg, val)	bus_write_4(sc->sge_res, reg, val)
217 	CSR_WRITE_4(sc, ROMInterface,
338 	CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
362 	CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
436 	CSR_WRITE_4(sc, StationControl, ctl);
438 		CSR_WRITE_4(sc, RGMIIDelay, 0x0441);
439 		CSR_WRITE_4(sc, RGMIIDelay, 0x0440);
480 	CSR_WRITE_4(sc, RxHashTable, hashes[0]);
481 	CSR_WRITE_4(sc, RxHashTable2, hashes[1]);
507 	CSR_WRITE_4(sc, IntrMask, 0);
508 	CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
511 	CSR_WRITE_4(sc, IntrControl, 0x8000);
514 	CSR_WRITE_4(sc, IntrControl, 0);
516 	CSR_WRITE_4(sc, TX_CTL, 0x1a00);
517 	CSR_WRITE_4(sc, RX_CTL, 0x1a00);
519 	CSR_WRITE_4(sc, IntrMask, 0);
520 	CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
522 	CSR_WRITE_4(sc, GMIIControl, 0);
1345 	CSR_WRITE_4(sc, IntrStatus, status);
1347 	CSR_WRITE_4(sc, IntrMask, 0);
1364 				CSR_WRITE_4(sc, RX_CTL,
1373 		CSR_WRITE_4(sc, IntrStatus, status);
1377 		CSR_WRITE_4(sc, IntrMask, SGE_INTRS);
1605 		CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB | TX_CTL_POLL);
1651 	CSR_WRITE_4(sc, TX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_tx_paddr));
1652 	CSR_WRITE_4(sc, RX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_rx_paddr));
1654 	CSR_WRITE_4(sc, TxMacControl, 0x60);
1655 	CSR_WRITE_4(sc, RxWakeOnLan, 0);
1656 	CSR_WRITE_4(sc, RxWakeOnLanData, 0);
1674 		CSR_WRITE_4(sc, StationControl, 0x04008001);
1676 		CSR_WRITE_4(sc, StationControl, 0x04000001);
1680 	CSR_WRITE_4(sc, IntrControl, 0x08880000);
1683 		CSR_WRITE_4(sc, IntrControl, sc->sge_intrcontrol);
1685 		CSR_WRITE_4(sc, IntrTimer, sc->sge_intrtimer);
1691 	CSR_WRITE_4(sc, IntrStatus, 0xFFFFFFFF);
1692 	CSR_WRITE_4(sc, IntrMask, SGE_INTRS);
1695 	CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB);
1696 	CSR_WRITE_4(sc, RX_CTL, 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB);
1889 	CSR_WRITE_4(sc, IntrMask, 0);
1891 	CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
1893 	CSR_WRITE_4(sc, TX_CTL, 0x1a00);
1894 	CSR_WRITE_4(sc, RX_CTL, 0x1a00);
1897 	CSR_WRITE_4(sc, IntrMask, 0);
1898 	CSR_WRITE_4(sc, IntrStatus, 0xffffffff);