/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonTargetTransformInfo.cpp | 53 EVT VecVT = EVT::getEVT(VecTy); 54 if (!VecVT.isSimple() || VecVT.getSizeInBits() <= 64) 56 if (ST.isHVXVectorType(VecVT.getSimpleVT())) 58 auto Action = TLI.getPreferredVectorAction(VecVT.getSimpleVT());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypesGeneric.cpp | 368 EVT VecVT = N->getValueType(0); local 369 unsigned NumElts = VecVT.getVectorNumElements(); 374 assert(OldVT == VecVT.getVectorElementType() && 395 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); 406 EVT VecVT = N->getValueType(0); local 407 unsigned NumElts = VecVT.getVectorNumElements(); 414 assert(OldEVT == VecVT.getVectorElementType() && 437 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
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H A D | LegalizeVectorTypes.cpp | 1132 EVT VecVT = Vec.getValueType(); local 1133 unsigned VecElems = VecVT.getVectorNumElements(); 1153 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1158 SDValue SubVecPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); 1159 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 1360 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, ResNE); local 1361 return DAG.getBuildVector(VecVT, dl, Scalars); 1432 EVT VecVT = Vec.getValueType(); 1433 EVT EltVT = VecVT.getVectorElementType(); 1434 if (VecVT 2061 EVT VecVT = VecOp.getValueType(); local 2171 EVT VecVT = Vec.getValueType(); local [all...] |
H A D | LegalizeDAG.cpp | 1330 EVT VecVT = Vec.getValueType(); 1334 StackPtr = DAG.CreateStackTemporary(VecVT); 1339 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); 1349 VecVT.getVectorElementType()); 1373 EVT VecVT = Vec.getValueType(); 1374 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1383 SDValue SubStackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
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H A D | DAGCombiner.cpp | 17066 EVT VecVT = VecOp.getValueType(); local 17078 return VecVT.isInteger() ? DAG.getAnyExtOrTrunc(Elt, DL, ScalarVT) : Elt; 17096 unsigned NumElts = VecVT.getVectorNumElements(); 17102 TLI.isTypeLegal(VecVT) && 17103 (VecOp.hasOneUse() || TLI.aggressivelyPreferBuildVectorSources(VecVT))) { 17118 if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() && 17138 unsigned VecEltBitWidth = VecVT.getScalarSizeInBits(); 17194 TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, VecVT) || 17195 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { 17228 EVT ExtVT = VecVT 17617 EVT VecVT = Extract.getOperand(0).getValueType(); local 18029 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SVT, local [all...] |
H A D | TargetLowering.cpp | 754 EVT VecVT = Vec.getValueType(); local 755 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) && 887 EVT VecVT = Vec.getValueType(); local 892 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) { 6989 EVT VecVT, 6995 unsigned NElts = VecVT.getVectorNumElements(); 7008 SDValue VecPtr, EVT VecVT, 7014 EVT EltVT = VecVT.getVectorElementType(); 7021 Index = clampDynamicVectorIndex(DAG, Index, VecVT, dl);
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H A D | LegalizeFloatTypes.cpp | 2202 EVT VecVT = Vec->getValueType(0); local 2203 EVT EltVT = VecVT.getVectorElementType(); 2207 switch (getTypeAction(VecVT)) {
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H A D | SelectionDAG.cpp | 3245 EVT VecVT = InVec.getValueType(); 3246 const unsigned EltBitWidth = VecVT.getScalarSizeInBits(); 3247 const unsigned NumSrcElts = VecVT.getVectorNumElements(); 3895 EVT VecVT = InVec.getValueType(); 3898 const unsigned NumSrcElts = VecVT.getVectorNumElements(); 9318 EVT VecVT = EVT::getVectorVT(*getContext(), EltVT, ResNE); 9319 return getBuildVector(VecVT, dl, Scalars);
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H A D | LegalizeIntegerTypes.cpp | 1468 EVT VecVT = N->getValueType(0); local 1469 unsigned NumElts = VecVT.getVectorNumElements(); 1470 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 3925 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC, argument 3930 if (VecVT.isFloatingPoint()) { 3953 if (VecVT == MVT::v4f32) 3955 else if (VecVT == MVT::v2f64) 3960 if (VecVT == MVT::v4f32) 3962 else if (VecVT == MVT::v2f64) 3967 if (VecVT == MVT::v4f32) 3969 else if (VecVT == MVT::v2f64) 3997 if (VecVT == MVT::v16i8) 3999 else if (VecVT [all...] |
H A D | PPCISelLowering.cpp | 7995 EVT VecVT = Vec.getValueType(); local 7996 assert(VecVT.isVector() && "Expected a vector type."); 7997 assert(VecVT.getSizeInBits() < 128 && "Vector is already full width."); 7999 EVT EltVT = VecVT.getVectorElementType(); 8003 unsigned NumConcat = WideNumElts / VecVT.getVectorNumElements(); 8006 SDValue UndefVec = DAG.getUNDEF(VecVT); 8550 EVT VecVT = V->getValueType(0); local 8551 bool RightType = VecVT == MVT::v2f64 || 8552 (HasP8Vector && VecVT == MVT::v4f32) || 8553 (HasDirectMove && (VecVT [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 721 VecVT = MVT::getVectorVT(MVT::getIntegerVT(8), 16); 734 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize), 747 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize), 4998 EVT VecVT = Op0.getValueType(); 5003 unsigned Mask = VecVT.getVectorNumElements() - 1; 5010 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); 5440 // Try to simplify an EXTRACT_VECTOR_ELT from a vector of type VecVT 5442 // of the input vector and Index is the index (based on type VecVT) that 5446 EVT VecVT, SDValue Op, 5453 unsigned BytesPerElement = VecVT 5445 combineExtract(const SDLoc &DL, EVT ResVT, EVT VecVT, SDValue Op, unsigned Index, DAGCombinerInfo &DCI, bool Force) const argument 5559 EVT VecVT = Vec.getValueType(); local 5881 EVT VecVT = Op.getValueType(); local 5897 EVT VecVT = Op0.getValueType(); local 6120 EVT VecVT = N->getValueType(0); local 6149 EVT VecVT = N->getValueType(0); local [all...] |
H A D | SystemZISelLowering.h | 615 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, 695 MVT VecVT; member in struct:llvm::SystemZVectorConstantInfo
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H A D | SystemZISelDAGToDAG.cpp | 1152 assert(VCI.VecVT.getSizeInBits() == 128 && "Expected a vector type"); 1158 SDValue Op = CurDAG->getNode(VCI.Opcode, DL, VCI.VecVT, Ops); 1160 if (VCI.VecVT == VT.getSimpleVT())
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 3622 MVT VecVT = MVT::Other; 3627 VecVT = MVT::v16f32; 3629 VecVT = MVT::v8f32; 3631 VecVT = MVT::v4f32; 3637 if (VecVT != MVT::Other) 3638 RegParmTypes.push_back(VecVT); 5139 EVT VecVT = VecOp.getValueType(); 5140 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT)) 5145 EVT ScalarVT = VecVT.getScalarType(); 8249 MVT VecVT [all...] |
H A D | X86ISelDAGToDAG.cpp | 427 MVT VecVT = N->getOperand(0).getSimpleValueType(); local 428 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); 435 MVT VecVT = N->getSimpleValueType(0); local 436 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); 952 MVT VecVT = VT == MVT::f64 ? MVT::v2f64 : MVT::v4f32; local 954 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, 956 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, 961 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); 973 Res = CurDAG->getNode(ISD::BITCAST, dl, VecVT, Res); 975 Res = CurDAG->getNode(N->getOpcode(), dl, VecVT, Op [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.h | 193 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
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H A D | SIISelLowering.cpp | 4788 EVT VecVT = Vec.getValueType(); local 4790 EVT EltVT = VecVT.getVectorElementType(); 4798 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt, 4809 EVT VecVT = Vec.getValueType(); local 4810 EVT EltVT = VecVT.getVectorElementType(); 4811 unsigned VecSize = VecVT.getSizeInBits(); 4817 unsigned NumElts = VecVT.getVectorNumElements(); 4845 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat); 4859 DAG.getSplatBuildVector(VecVT, SL, InsVal)); 4877 return DAG.getNode(ISD::BITCAST, SL, VecVT, BF 9283 EVT VecVT = Vec.getValueType(); local 9403 EVT VecVT = Vec.getValueType(); local [all...] |
H A D | R600ISelLowering.cpp | 697 EVT VecVT = Vector.getValueType(); local 698 EVT EltVT = VecVT.getVectorElementType(); 701 for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) { 707 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
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H A D | AMDGPUISelLowering.cpp | 761 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 5700 EVT VecVT = EVT::getVectorVT( local 5703 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc); 7306 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), IVT, NumElts); local 7307 SDValue Val = DAG.getBuildVector(VecVT, dl, Ops); 7357 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); local 7361 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); 8111 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); local 8112 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); 8113 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); 8124 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Op 8144 EVT VecVT = Op.getOperand(0).getValueType(); local 8191 EVT VecVT = VecIn.getValueType(); local 8207 EVT VecVT = Op.getOperand(0).getValueType(); local 12904 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); local 15719 EVT VecVT = SrcSV.getValueType(); local [all...] |
H A D | ARMISelDAGToDAG.cpp | 3728 EVT VecVT = N->getValueType(0); local 3729 EVT EltVT = VecVT.getVectorElementType(); 3730 unsigned NumElts = VecVT.getVectorNumElements(); 3734 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); 3740 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); 3745 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 5095 EVT VecVT; local 5101 VecVal1 = DAG.getTargetInsertSubreg(Idx, DL, VecVT, 5102 DAG.getUNDEF(VecVT), In1); 5103 VecVal2 = DAG.getTargetInsertSubreg(Idx, DL, VecVT, 5104 DAG.getUNDEF(VecVT), In2); 5106 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); 5107 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); 5112 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32); 5116 VecVT = MVT::v2i64; 5125 VecVT 8052 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 2595 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const { 4175 /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of 4178 SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 2586 EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts); local 2593 DAG.getLoad(VecVT, dl, Root, VecAddr,
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