Searched refs:UMUL_LOHI (Results 1 - 25 of 30) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16ISelDAGToDAG.cpp196 case ISD::UMUL_LOHI: {
197 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
H A DMipsSEISelLowering.cpp184 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
195 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
231 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
278 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
455 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h204 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
207 SMUL_LOHI, UMUL_LOHI, enumerator in enum:llvm::ISD::NodeType
H A DTargetLowering.h2247 case ISD::UMUL_LOHI:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp540 case ISD::UMUL_LOHI:
H A DAVRISelLowering.cpp165 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
171 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h92 UMUL_LOHI,
H A DSystemZISelLowering.cpp208 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
3453 // Do a full 128-bit multiplication based on SystemZISD::UMUL_LOHI:
3471 // SystemZISD::UMUL_LOHI returns the low result in the odd register and
3474 lowerGR128Binary(DAG, DL, VT, SystemZISD::UMUL_LOHI,
3495 // SystemZISD::UMUL_LOHI returns the low result in the odd register and
3496 // the high result in the even register. ISD::UMUL_LOHI is defined to
3498 lowerGR128Binary(DAG, DL, VT, SystemZISD::UMUL_LOHI,
5129 case ISD::UMUL_LOHI:
5320 OPCODE(UMUL_LOHI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp99 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
211 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
559 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp3312 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3321 case ISD::UMUL_LOHI:
3327 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3360 // UMUL_LOHI, form a preference by checking which forms of plain
3363 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3370 OpToUse = ISD::UMUL_LOHI;
3374 OpToUse = ISD::UMUL_LOHI;
4360 case ISD::UMUL_LOHI:
4363 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
H A DSelectionDAGDumper.cpp235 case ISD::UMUL_LOHI: return "umul_lohi";
H A DTargetLowering.cpp4905 if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT)
4906 : isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
4908 DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y);
5743 assert(Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI ||
5753 isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
5771 Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R);
7235 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
7500 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
H A DLegalizeVectorOps.cpp447 case ISD::UMUL_LOHI:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp92 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp126 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Promote);
131 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp113 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1431 ISD::SMUL_LOHI, ISD::UMUL_LOHI}) {
1476 ISD::UADDO, ISD::SSUBO, ISD::USUBO, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1655 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1669 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp319 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
383 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2036 case ISD::UMUL_LOHI:
4770 case ISD::UMUL_LOHI: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp145 setOperationAction(ISD::UMUL_LOHI, XLenVT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp737 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
1063 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
4439 // We generate a UMUL_LOHI and then check if the high word is 0.
4441 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
11284 if (V->getOpcode() == ISD::UMUL_LOHI ||
11371 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
11372 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
11376 // UMUL_LOHI
11385 // and the add to the low part of the result of ISD::UMUL_LOHI adds or subtracts
11417 // Check that the ADDC adds the low result of the S/UMUL_LOHI
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp515 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp279 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
280 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
282 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
679 setOperationAction(ISD::UMUL_LOHI, VT, Expand);

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