Searched refs:UDIVREM (Results 1 - 25 of 27) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h209 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
211 SDIVREM, UDIVREM, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h94 UDIVREM,
H A DSystemZISelLowering.cpp171 setOperationAction(ISD::UDIVREM, VT, Custom);
3533 lowerGR128Binary(DAG, DL, VT, SystemZISD::UDIVREM,
5133 case ISD::UDIVREM:
5322 OPCODE(UDIVREM);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp155 setOperationAction(ISD::UDIVREM, VT, Custom);
341 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
706 case ISD::UDIVREM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp87 setOperationAction(ISD::UDIVREM, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp237 case ISD::UDIVREM: return "udivrem";
H A DLegalizeIntegerTypes.cpp3649 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
3650 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3676 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
3677 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
H A DLegalizeDAG.cpp3280 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3299 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
4173 case ISD::UDIVREM:
H A DLegalizeVectorOps.cpp376 case ISD::UDIVREM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp199 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
206 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
239 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
286 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
460 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
H A DMipsISelLowering.cpp499 setTargetDAGCombine(ISD::UDIVREM);
1162 case ISD::UDIVREM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp134 setOperationAction(ISD::UDIVREM, MVT::i8, Promote);
140 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp315 setOperationAction(ISD::UDIVREM, VT, Custom);
385 setOperationAction(ISD::UDIVREM, VT, Expand);
1133 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
1660 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
2007 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
H A DR600ISelLowering.cpp686 case ISD::UDIVREM: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp982 case ISD::UDIVREM:
H A DARMISelLowering.cpp1189 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1191 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1194 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
9373 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
9444 case ISD::UDIVREM:
16193 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
16211 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
16238 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp109 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp114 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1429 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1475 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1498 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1505 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp143 setOperationAction(ISD::UDIVREM, XLenVT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3477 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
H A DX86ISelDAGToDAG.cpp4861 case ISD::UDIVREM: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp363 setOperationAction(ISD::UDIVREM, VT, Expand);
367 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
368 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp279 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
284 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
286 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
681 setOperationAction(ISD::UDIVREM, VT, Expand);

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