/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 209 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 211 SDIVREM, UDIVREM, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.h | 94 UDIVREM,
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H A D | SystemZISelLowering.cpp | 171 setOperationAction(ISD::UDIVREM, VT, Custom); 3533 lowerGR128Binary(DAG, DL, VT, SystemZISD::UDIVREM, 5133 case ISD::UDIVREM: 5322 OPCODE(UDIVREM);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 155 setOperationAction(ISD::UDIVREM, VT, Custom); 341 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && 706 case ISD::UDIVREM:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 87 setOperationAction(ISD::UDIVREM, VT, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 237 case ISD::UDIVREM: return "udivrem";
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H A D | LegalizeIntegerTypes.cpp | 3649 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) { 3650 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops); 3676 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) { 3677 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
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H A D | LegalizeDAG.cpp | 3280 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3299 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 4173 case ISD::UDIVREM:
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H A D | LegalizeVectorOps.cpp | 376 case ISD::UDIVREM:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 199 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); 206 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 239 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 286 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 460 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
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H A D | MipsISelLowering.cpp | 499 setTargetDAGCombine(ISD::UDIVREM); 1162 case ISD::UDIVREM:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 134 setOperationAction(ISD::UDIVREM, MVT::i8, Promote); 140 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 315 setOperationAction(ISD::UDIVREM, VT, Custom); 385 setOperationAction(ISD::UDIVREM, VT, Expand); 1133 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); 1660 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), 2007 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
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H A D | R600ISelLowering.cpp | 686 case ISD::UDIVREM: {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 982 case ISD::UDIVREM:
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H A D | ARMISelLowering.cpp | 1189 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 1191 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); 1194 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 9373 case ISD::UDIVREM: return LowerDivRem(Op, DAG); 9444 case ISD::UDIVREM: 16193 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || 16211 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || 16238 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 109 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 114 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1429 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, 1475 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1498 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 1505 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 143 setOperationAction(ISD::UDIVREM, XLenVT, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 3477 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
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H A D | X86ISelDAGToDAG.cpp | 4861 case ISD::UDIVREM: {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 363 setOperationAction(ISD::UDIVREM, VT, Expand); 367 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 368 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 279 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 284 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 286 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 681 setOperationAction(ISD::UDIVREM, VT, Expand);
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