/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyLowerBrUnless.cpp | 62 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 81 Def->setDesc(TII.get(NE_I32)); 85 Def->setDesc(TII.get(EQ_I32)); 89 Def->setDesc(TII.get(LE_S_I32)); 93 Def->setDesc(TII.get(LT_S_I32)); 97 Def->setDesc(TII.get(GE_S_I32)); 101 Def->setDesc(TII.get(GT_S_I32)); 105 Def->setDesc(TII.get(LE_U_I32)); 109 Def->setDesc(TII.get(LT_U_I32)); 113 Def->setDesc(TII [all...] |
H A D | WebAssemblyFrameLowering.cpp | 128 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 132 BuildMI(MBB, InsertStore, DL, TII->get(WebAssembly::GLOBAL_SET_I32)) 143 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 144 if (I->getOpcode() == TII->getCallFrameDestroyOpcode() && 163 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 180 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::GLOBAL_GET_I32), SPReg) 188 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), BasePtr) 194 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) 196 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::SUB_I32), 206 BuildMI(MBB, InsertPt, DL, TII 230 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | PseudoSourceValue.cpp | 27 PseudoSourceValue::PseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII) argument 29 AddressSpace = TII.getAddressSpaceForPseudoSourceKind(Kind); 83 unsigned Kind, const TargetInstrInfo &TII) 84 : PseudoSourceValue(Kind, TII) {} 100 const TargetInstrInfo &TII) 101 : CallEntryPseudoSourceValue(GlobalValueCallEntry, TII), GV(GV) {} 103 const char *ES, const TargetInstrInfo &TII) 104 : CallEntryPseudoSourceValue(ExternalSymbolCallEntry, TII), ES(ES) {} 108 : TII(TIInfo), 109 StackPSV(PseudoSourceValue::Stack, TII), 82 CallEntryPseudoSourceValue( unsigned Kind, const TargetInstrInfo &TII) argument 98 GlobalValuePseudoSourceValue( const GlobalValue *GV, const TargetInstrInfo &TII) argument 102 ExternalSymbolPseudoSourceValue( const char *ES, const TargetInstrInfo &TII) argument [all...] |
H A D | PostRAHazardRecognizer.cpp | 70 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo(); local 72 TII->CreateTargetPostRAHazardRecognizer(Fn)); 87 TII->insertNoop(MBB, MachineBasicBlock::iterator(MI));
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H A D | FEntryInserter.cpp | 44 auto *TII = MF.getSubtarget().getInstrInfo(); local 46 TII->get(TargetOpcode::FENTRY_CALL));
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H A D | PatchableFunction.cpp | 60 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local 63 TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER)); 67 TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER)); 86 auto *TII = MF.getSubtarget().getInstrInfo(); local 88 TII->get(TargetOpcode::PATCHABLE_OP))
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H A D | XRayInstrumentation.cpp | 70 const TargetInstrInfo *TII, 82 const TargetInstrInfo *TII, 89 MachineFunction &MF, const TargetInstrInfo *TII, 98 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) { 103 if (TII->isTailCall(T) && op.HandleTailcall) { 109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)) 125 MachineFunction &MF, const TargetInstrInfo *TII, 131 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) { 134 if (TII->isTailCall(T) && op.HandleTailcall) { 140 BuildMI(MBB, T, T.getDebugLoc(), TII 88 replaceRetWithPatchableRet( MachineFunction &MF, const TargetInstrInfo *TII, InstrumentationOptions op) argument 124 prependRetWithPatchableExit( MachineFunction &MF, const TargetInstrInfo *TII, InstrumentationOptions op) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ExpandSpecialInstrs.cpp | 41 const R600InstrInfo *TII = nullptr; member in class:__anon2105::R600ExpandSpecialInstrsPass 75 int OpIdx = TII->getOperandIdx(*OldMI, Op); 78 TII->setImmOperand(*NewMI, Op, Val); 84 TII = ST.getInstrInfo(); 86 const R600RegisterInfo &TRI = TII->getRegisterInfo(); 97 if (TII->isLDSRetInstr(MI.getOpcode())) { 98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); 101 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, 104 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), 106 int MovPredSelIdx = TII [all...] |
H A D | SIAddIMGInit.cpp | 65 const SIInstrInfo *TII = ST.getInstrInfo(); local 78 if (TII->isMIMG(Opcode) && !MI.mayStore()) { 79 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe); 80 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe); 81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16); 103 TII->getNamedOperand(MI, AMDGPU::OpName::dmask); 112 TII->isGather4(Opcode) ? 4 : countPopulation(dmask); 127 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; 133 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); 144 BuildMI(MBB, MI, DL, TII [all...] |
H A D | SIPeepholeSDWA.cpp | 75 const SIInstrInfo *TII; member in class:__anon2129::SIPeepholeSDWA 121 virtual MachineInstr *potentialToConvert(const SIInstrInfo *TII) = 0; 122 virtual bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) = 0; 154 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override; 155 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override; 162 uint64_t getSrcMods(const SIInstrInfo *TII, 181 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override; 182 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override; 202 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override; 330 uint64_t SDWASrcOperand::getSrcMods(const SIInstrInfo *TII, argument 355 potentialToConvert(const SIInstrInfo *TII) argument 365 convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) argument 439 potentialToConvert(const SIInstrInfo *TII) argument 458 convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) argument 488 convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) argument [all...] |
H A D | SIModeRegister.cpp | 144 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII); 146 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII); 148 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII); 150 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII); 153 const SIInstrInfo *TII, Status InstrMode); 171 const SIInstrInfo *TII) { 172 if (TII->usesFPDPRounding(MI)) { 193 const SIInstrInfo *TII, Status InstrMode) { 198 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32)) 228 const SIInstrInfo *TII) { 170 getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII) argument 192 insertSetreg(MachineBasicBlock &MBB, MachineInstr *MI, const SIInstrInfo *TII, Status InstrMode) argument 227 processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII) argument 326 processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII) argument 362 processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII) argument 378 const SIInstrInfo *TII = ST.getInstrInfo(); local [all...] |
H A D | AMDGPUMacroFusion.cpp | 32 const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_); local 47 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI,
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H A D | R600Packetizer.cpp | 57 const R600InstrInfo *TII; member in class:__anon2107::R600PacketizerList 72 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) 84 if (TII->isPredicated(*BI)) 86 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); 89 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); 94 if (isTrans || TII->isTransOnly(*BI)) { 136 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]); 150 TII(ST.getInstrInfo()), 151 TRI(TII->getRegisterInfo()) { 169 if (TII 327 const R600InstrInfo *TII = ST.getInstrInfo(); local [all...] |
H A D | R600ClauseMergePass.cpp | 47 const R600InstrInfo *TII; member in class:__anon2488::R600ClauseMergePass 87 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) 94 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) 100 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); 119 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); 123 if (CumuledInsts >= TII->getMaxAlusPerClause()) { 131 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); 133 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); 135 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); 147 TII [all...] |
H A D | SIFoldOperands.cpp | 89 const SIInstrInfo *TII; member in class:__anon2113::SIFoldOperands 134 static bool isInlineConstantIfFolded(const SIInstrInfo *TII, argument 138 if (TII->isInlineConstant(UseMI, OpNo, OpToFold)) 159 const MCInstrDesc &MadDesc = TII->get(Opc); 160 return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType); 171 static bool frameIndexMayFold(const SIInstrInfo *TII, argument 176 (TII->isMUBUF(UseMI) || TII->isFLATScratch(UseMI)) && 185 const SIInstrInfo &TII, 216 switch (TII 184 updateOperand(FoldCandidate &Fold, const SIInstrInfo &TII, const TargetRegisterInfo &TRI, const GCNSubtarget &ST) argument 328 tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList, MachineInstr *MI, unsigned OpNo, MachineOperand *OpToFold, const SIInstrInfo *TII) argument 460 isUseSafeToFold(const SIInstrInfo *TII, const MachineInstr &MI, const MachineOperand &UseMO) argument 470 getRegSeqInit( SmallVectorImpl<std::pair<MachineOperand*, unsigned>> &Defs, Register UseReg, uint8_t OpTy, const SIInstrInfo *TII, const MachineRegisterInfo &MRI) argument 503 tryToFoldACImm(const SIInstrInfo *TII, const MachineOperand &OpToFold, MachineInstr *UseMI, unsigned UseOpIdx, SmallVectorImpl<FoldCandidate> &FoldList) argument 987 tryConstantFoldOp(MachineRegisterInfo &MRI, const SIInstrInfo *TII, MachineInstr *MI, MachineOperand *ImmOp) argument 1101 tryFoldInst(const SIInstrInfo *TII, MachineInstr *MI) argument [all...] |
H A D | SIShrinkInstructions.cpp | 71 static bool foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, argument 73 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI)); 116 if (TII->commuteInstruction(MI)) { 117 if (foldImmediates(MI, TII, MRI, false)) 121 TII->commuteInstruction(MI); 128 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { argument 130 !TII->isInlineConstant(*Src.getParent(), 134 static bool isKUImmOperand(const SIInstrInfo *TII, cons argument 140 isKImmOrKUImmOperand(const SIInstrInfo *TII, const MachineOperand &Src, bool &IsUnsigned) argument 158 isReverseInlineImm(const SIInstrInfo *TII, const MachineOperand &Src, int32_t &ReverseImm) argument 182 shrinkScalarCompare(const SIInstrInfo *TII, MachineInstr &MI) argument 228 const SIInstrInfo *TII = ST.getInstrInfo(); local 315 shrinkScalarLogicOp(const GCNSubtarget &ST, MachineRegisterInfo &MRI, const SIInstrInfo *TII, MachineInstr &MI) argument 455 matchSwap(MachineInstr &MovT, MachineRegisterInfo &MRI, const SIInstrInfo *TII) argument 555 const SIInstrInfo *TII = ST.getInstrInfo(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64A53Fix835769.cpp | 80 const TargetInstrInfo *TII; member in class:__anon2380::AArch64A53Fix835769 120 TII = F.getSubtarget().getInstrInfo(); 131 const TargetInstrInfo *TII) { 144 if (S == PrevBB && !TII->analyzeBranch(*PrevBB, TBB, FBB, Cond) && !TBB && 156 const TargetInstrInfo *TII) { 161 while ((FMBB = getBBFallenThrough(FMBB, TII))) { 172 const TargetInstrInfo *TII) { 176 MachineInstr *I = getLastNonPseudo(MBB, TII); 179 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0); 183 BuildMI(MBB, MI, DL, TII 130 getBBFallenThrough(MachineBasicBlock *MBB, const TargetInstrInfo *TII) argument 155 getLastNonPseudo(MachineBasicBlock &MBB, const TargetInstrInfo *TII) argument 171 insertNopBeforeInstruction(MachineBasicBlock &MBB, MachineInstr* MI, const TargetInstrInfo *TII) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.cpp | 45 const MSP430InstrInfo &TII = local 66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) 70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) 98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) 110 const MSP430InstrInfo &TII = local 135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); 157 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP); 161 TII.get(MSP430::SUB16ri), MSP430::SP) 170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) 191 const TargetInstrInfo &TII local 217 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local 228 const MSP430InstrInfo &TII = local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEFrameLowering.cpp | 41 const VEInstrInfo &TII = local 51 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) 55 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) 59 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) 63 BuildMI(MBB, MBBI, dl, TII.get(VE::STSri)) 67 BuildMI(MBB, MBBI, dl, TII.get(VE::ORri), VE::SX9) 79 const VEInstrInfo &TII = local 89 BuildMI(MBB, MBBI, dl, TII.get(VE::ORri), VE::SX11) 92 BuildMI(MBB, MBBI, dl, TII.get(VE::LDSri), VE::SX16) 95 BuildMI(MBB, MBBI, dl, TII 111 const VEInstrInfo &TII = local 141 const VEInstrInfo &TII = local 179 const VEInstrInfo &TII = local [all...] |
H A D | VEInstrInfo.cpp | 57 const VEInstrInfo &TII = local 94 BuildMI(BB, dl, TII.get(VE::BCRLrr)) 105 BuildMI(BB, dl, TII.get(VE::LDSri), VE::SX61) 108 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62) 111 BuildMI(BB, dl, TII.get(VE::LEAzzi), VE::SX63) 113 BuildMI(BB, dl, TII.get(VE::SHMri)) 117 BuildMI(BB, dl, TII.get(VE::SHMri)) 121 BuildMI(BB, dl, TII.get(VE::SHMri)) 125 BuildMI(BB, dl, TII.get(VE::MONC)); 127 BuildMI(BB, dl, TII [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonHazardRecognizer.cpp | 41 if (!MI || TII->isZeroCost(MI->getOpcode())) 47 if (TII->mayBeNewStore(*MI)) { 57 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)), 119 if (TII->isZeroCost(MI->getOpcode())) 125 assert(TII->mayBeNewStore(*MI) && "Expecting .new store"); 128 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)), 142 if (TII->mayBeCurLoad(*MI)) 157 if (TII [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsInstructionSelector.cpp | 55 const MipsInstrInfo &TII; member in class:__anon2325::MipsInstructionSelector 77 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()), 107 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 146 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); 152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); 159 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); 167 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) 169 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) 266 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) 270 if (!constrainSelectedInstRegOperands(*Mul, TII, TR [all...] |
H A D | Mips16FrameLowering.cpp | 45 const Mips16InstrInfo &TII = local 62 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI); 67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 82 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 87 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0) 95 const Mips16InstrInfo &TII = local 104 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP) 109 TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI); 166 const Mips16InstrInfo &TII = local 168 const MipsRegisterInfo &RI = TII [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachineLoopUtils.h | 38 const TargetInstrInfo *TII);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 47 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>( local 52 !(TII.getSubtarget().hasMuxedUnits() && LastMI->mayLoadOrStore()) && 61 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 62 (TII.canCauseFpMLxStall(MI->getOpcode()) || 63 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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