Target/AMDGPU/SIFoldOperands.cpp

89   const SIInstrInfo *TII;
134 static bool isInlineConstantIfFolded(const SIInstrInfo *TII,
138   if (TII->isInlineConstant(UseMI, OpNo, OpToFold))
159       const MCInstrDesc &MadDesc = TII->get(Opc);
160       return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
171 static bool frameIndexMayFold(const SIInstrInfo *TII,
176     (TII->isMUBUF(UseMI) || TII->isFLATScratch(UseMI)) &&
185                           const SIInstrInfo &TII,
216       switch (TII.get(Opcode).OpInfo[OpNo].OperandType) {
259     MachineInstr *Inst32 = TII.buildShrunkInst(*MI, Op32);
262       BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg())
275     MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF));
278       TII.commuteInstruction(*Inst32, false);
331                              const SIInstrInfo *TII) {
332   if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {
348       MI->setDesc(TII->get(NewOpc));
349       bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII);
354       MI->setDesc(TII->get(Opc));
359       MI->setDesc(TII->get(AMDGPU::S_SETREG_IMM32_B32));
376     bool CanCommute = TII->findCommutedOpIndices(*MI, CommuteIdx0, CommuteIdx1);
395         !TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1))
398     if (!TII->isOperandLegal(*MI, CommuteOpNo, OpToFold)) {
410             !TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg()))
423       TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1);
433   if (TII->isSALU(MI->getOpcode())) {
436     const SIRegisterInfo &SRI = TII->getRegisterInfo();
441           !TII->isInlineConstant(*OpToFold, OpInfo)) {
446               TII->isLiteralConstantLike(Op, OpInfo)) {
460 static bool isUseSafeToFold(const SIInstrInfo *TII,
463   return !UseMO.isUndef() && !TII->isSDWA(MI);
473     const SIInstrInfo *TII, const MachineRegisterInfo &MRI) {
484          TII->isFoldableCopy(*SubDef);
488         if (TII->isInlineConstant(*Op, OpTy))
503 static bool tryToFoldACImm(const SIInstrInfo *TII,
518   if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) &&
519       TII->isOperandLegal(*UseMI, UseOpIdx, &OpToFold)) {
537   if (!getRegSeqInit(Defs, UseReg, OpTy, TII, MRI))
549       if (!TII->isInlineConstant(*Op, OpTy) ||
550           !TII->isOperandLegal(*UseMI, UseOpIdx, Op))
571   if (!isUseSafeToFold(TII, *UseMI, UseOp))
595       if (tryToFoldACImm(TII, UseMI->getOperand(0), RSUseMI,
609   if (tryToFoldACImm(TII, OpToFold, UseMI, UseOpIdx, FoldList))
612   if (frameIndexMayFold(TII, *UseMI, UseOpIdx, OpToFold)) {
615     MachineOperand *SOff = TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset);
620     if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() !=
667         TII->isInlineConstant(OpToFold, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
668       UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32));
677     unsigned MovOp = TII->getMovOpcode(DestRC);
681     UseMI->setDesc(TII->get(MovOp));
696       unsigned Size = TII->getOpSize(*UseMI, 1);
710           getRegSeqInit(Defs, UseReg, AMDGPU::OPERAND_REG_INLINE_C_INT32, TII,
715         UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE));
726               TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
731                     TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), Tmp).addImm(Imm);
757               BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def);
768               BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def);
773                     TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), Tmp).addReg(Vgpr);
787         UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32));
790         UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_READ_B32));
810         UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32));
833         UseMI->setDesc(TII->get(AMDGPU::COPY));
853     tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII);
883     tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII);
889   tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII);
988                               const SIInstrInfo *TII,
995     mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32)));
1014       bool UseCopy = TII->getNamedOperand(*MI, AMDGPU::OpName::src2)->isReg();
1018       MI->setDesc(TII->get(UseCopy ? AMDGPU::COPY : AMDGPU::V_MOV_B32_e32));
1031     const SIRegisterInfo &TRI = TII->getRegisterInfo();
1038     mutateCopyOp(*MI, TII->get(getMovOpc(IsSGPR)));
1057       mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
1061       mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_OR_B32)));
1074       mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_AND_B32)));
1078       mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
1092       mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
1101 static bool tryFoldInst(const SIInstrInfo *TII,
1108     const MachineOperand *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0);
1109     const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1);
1117           TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false));
1167       if (OpToFold.isImm() && tryConstantFoldOp(*MRI, TII, UseMI, &OpToFold)) {
1194       if (isInlineConstantIfFolded(TII, *UseMI, OpNo, OpToFold)) {
1196       } else if (frameIndexMayFold(TII, *UseMI, OpNo, OpToFold)) {
1241     if (updateOperand(Fold, *TII, *TRI, *ST)) {
1253       tryFoldInst(TII, Fold.UseMI);
1256       TII->commuteInstruction(*Fold.UseMI, false);
1270     if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm())
1274     const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1275     const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1283     if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
1287       = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm();
1289       = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm();
1326   if (TII->getClampMask(*Def) != TII->getClampMask(MI))
1329   MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp);
1390     const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1391     const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1403         TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) ||
1404         TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) ||
1405         TII->hasModifiersSet(MI, AMDGPU::OpName::omod) ||
1406         TII->hasModifiersSet(MI, AMDGPU::OpName::clamp))
1419     const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1420     const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1424         !TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) &&
1425         !TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) &&
1426         !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp) &&
1427         !TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
1448   MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod);
1454   if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp))
1471   TII = ST->getInstrInfo();
1472   TRI = &TII->getRegisterInfo();
1490       tryFoldInst(TII, &MI);
1492       if (!TII->isFoldableCopy(MI)) {