1320957Sdim//===--- AMDGPUMacroFusion.cpp - AMDGPU Macro Fusion ----------------------===// 2320957Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6320957Sdim// 7320957Sdim//===----------------------------------------------------------------------===// 8320957Sdim// 9320957Sdim/// \file This file contains the AMDGPU implementation of the DAG scheduling 10320957Sdim/// mutation to pair instructions back to back. 11320957Sdim// 12320957Sdim//===----------------------------------------------------------------------===// 13320957Sdim 14320957Sdim#include "AMDGPUMacroFusion.h" 15320957Sdim#include "AMDGPUSubtarget.h" 16320957Sdim#include "SIInstrInfo.h" 17341825Sdim#include "MCTargetDesc/AMDGPUMCTargetDesc.h" 18320957Sdim 19320957Sdim#include "llvm/CodeGen/MacroFusion.h" 20320957Sdim 21320957Sdimusing namespace llvm; 22320957Sdim 23320957Sdimnamespace { 24320957Sdim 25341825Sdim/// Check if the instr pair, FirstMI and SecondMI, should be fused 26320957Sdim/// together. Given SecondMI, when FirstMI is unspecified, then check if 27320957Sdim/// SecondMI may be part of a fused pair at all. 28320957Sdimstatic bool shouldScheduleAdjacent(const TargetInstrInfo &TII_, 29320957Sdim const TargetSubtargetInfo &TSI, 30320957Sdim const MachineInstr *FirstMI, 31320957Sdim const MachineInstr &SecondMI) { 32320957Sdim const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_); 33320957Sdim 34320957Sdim switch (SecondMI.getOpcode()) { 35320957Sdim case AMDGPU::V_ADDC_U32_e64: 36320957Sdim case AMDGPU::V_SUBB_U32_e64: 37320957Sdim case AMDGPU::V_CNDMASK_B32_e64: { 38320957Sdim // Try to cluster defs of condition registers to their uses. This improves 39320957Sdim // the chance VCC will be available which will allow shrinking to VOP2 40320957Sdim // encodings. 41320957Sdim if (!FirstMI) 42320957Sdim return true; 43320957Sdim 44344779Sdim const MachineBasicBlock &MBB = *FirstMI->getParent(); 45344779Sdim const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 46344779Sdim const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); 47320957Sdim const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, 48320957Sdim AMDGPU::OpName::src2); 49344779Sdim return FirstMI->definesRegister(Src2->getReg(), TRI); 50320957Sdim } 51320957Sdim default: 52320957Sdim return false; 53320957Sdim } 54320957Sdim 55320957Sdim return false; 56320957Sdim} 57320957Sdim 58320957Sdim} // end namespace 59320957Sdim 60320957Sdim 61320957Sdimnamespace llvm { 62320957Sdim 63320957Sdimstd::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation () { 64320957Sdim return createMacroFusionDAGMutation(shouldScheduleAdjacent); 65320957Sdim} 66320957Sdim 67320957Sdim} // end namespace llvm 68