Lines Matching refs:TII
144 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
146 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
148 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
150 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
153 const SIInstrInfo *TII, Status InstrMode);
171 const SIInstrInfo *TII) {
172 if (TII->usesFPDPRounding(MI)) {
193 const SIInstrInfo *TII, Status InstrMode) {
198 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32))
228 const SIInstrInfo *TII) {
239 Status InstrMode = getInstructionMode(MI, TII);
245 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm();
259 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change));
266 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm();
292 insertSetreg(MBB, InsertionPoint, TII,
316 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change));
327 const SIInstrInfo *TII) {
363 const SIInstrInfo *TII) {
369 insertSetreg(MBB, BlockInfo[ThisBlock]->FirstInsertionPoint, TII, Delta);
371 insertSetreg(MBB, &MBB.instr_front(), TII, Delta);
378 const SIInstrInfo *TII = ST.getInstrInfo();
385 processBlockPhase1(BB, TII);
393 processBlockPhase2(*Phase2List.front(), TII);
400 processBlockPhase3(BB, TII);