Lines Matching refs:TII
57 const R600InstrInfo *TII;
72 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
84 if (TII->isPredicated(*BI))
86 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write);
89 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst);
94 if (isTrans || TII->isTransOnly(*BI)) {
136 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]);
150 TII(ST.getInstrInfo()),
151 TRI(TII->getRegisterInfo()) {
169 if (TII->isVector(MI))
171 if (!TII->isALUInstr(MI.getOpcode()))
177 return TII->isLDSInstr(MI.getOpcode());
187 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel),
188 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel);
208 TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ);
210 TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ);
222 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last);
230 isTransSlot = TII->isTransOnly(MI);
237 !TII->isVectorOnly(MI) && VLIW5) {
251 if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) {
267 if (!TII->fitsReadPortLimitations(CurrentPacketMIs,
284 if (isTransSlot && TII->readsLDSSrcReg(MI))
302 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
307 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle);
319 if (TII->isTransOnly(MI))
327 const R600InstrInfo *TII = ST.getInstrInfo();
379 if (TII->isSchedulingBoundary(*std::prev(I), &*MBB, Fn))