/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 542 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 547 SIGN_EXTEND_INREG, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 186 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 188 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); 189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); 192 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 193 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); 194 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); 197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); 199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); 201 setOperationAction(ISD::SIGN_EXTEND_INREG, MV [all...] |
H A D | AMDGPUISelLowering.cpp | 1130 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 1167 case ISD::SIGN_EXTEND_INREG: 1624 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize); 1625 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize); 2773 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp); 4051 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
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H A D | SIISelLowering.cpp | 228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom); 229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom); 230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); 231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom); 232 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); 233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v3i16, Custom); 234 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom); 235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom); 740 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); 7319 Cvt = DAG.getNode(ISD::SIGN_EXTEND_INREG, S [all...] |
H A D | AMDGPUISelDAGToDAG.cpp | 895 case ISD::SIGN_EXTEND_INREG: 2009 case ISD::SIGN_EXTEND_INREG: {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 219 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action); 222 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); 972 case ISD::SIGN_EXTEND_INREG: 975 // SIGN_EXTEND_INREG, but for non-vector sign extends the result might be an 1024 case ISD::SIGN_EXTEND_INREG: 1301 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), 1341 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 137 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Custom); 199 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); 202 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); 1077 Elems[i] = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NTy, 1465 if (Op.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1555 case ISD::SIGN_EXTEND_INREG:
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H A D | HexagonISelDAGToDAG.cpp | 1453 case ISD::SIGN_EXTEND_INREG: { 1521 case ISD::SIGN_EXTEND_INREG: 1597 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
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H A D | HexagonISelLowering.cpp | 1352 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 1530 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); 1531 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); 1532 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom); 757 case ISD::SIGN_EXTEND_INREG:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 87 case ISD::SIGN_EXTEND_INREG: 590 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 879 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 966 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), 1176 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), 1575 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 1840 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 3453 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 3467 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 3479 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, d [all...] |
H A D | LegalizeTypes.h | 254 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, 275 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
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H A D | SelectionDAGDumper.cpp | 322 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
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H A D | LegalizeVectorOps.cpp | 107 /// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA. 438 case ISD::SIGN_EXTEND_INREG: 848 case ISD::SIGN_EXTEND_INREG:
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H A D | LegalizeDAG.cpp | 759 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 932 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1024 case ISD::SIGN_EXTEND_INREG: { 2833 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType, 2927 case ISD::SIGN_EXTEND_INREG: { 2935 // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
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H A D | LegalizeVectorTypes.cpp | 59 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 466 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT, 839 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 2695 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
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H A D | DAGCombiner.cpp | 1153 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 1165 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp, 1571 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 2487 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 3245 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 7744 TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) == 7746 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, 9661 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 9667 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Op, 10378 // Special case: SIGN_EXTEND_INREG i [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 990 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim, 1246 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 403 // Some SIGN_EXTEND_INREG can be done using cvt instruction. 405 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal); 406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); 408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 4586 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 489 N.getOpcode() == ISD::SIGN_EXTEND_INREG) { 491 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG) 1665 assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG); 1880 case ISD::SIGN_EXTEND_INREG: 3076 case ISD::SIGN_EXTEND_INREG:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1490 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 1491 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 1492 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 217 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 428 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 686 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 977 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal); 978 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal); 979 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal); 980 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); 981 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); 982 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); 983 setOperationAction(ISD::SIGN_EXTEND_INREG, MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 115 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 875 SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp,
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