| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 209 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
211 SDIVREM, UDIVREM, enumerator in enum:llvm::ISD::NodeType
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 156 setOperationAction(ISD::SDIVREM, VT, Custom);
341 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
343 bool IsSigned = (Opcode == ISD::SDIVREM);
705 case ISD::SDIVREM:
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 93 SDIVREM,
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| H A D | SystemZISelLowering.cpp | 170 setOperationAction(ISD::SDIVREM, VT, Custom);
3521 lowerGR128Binary(DAG, DL, VT, SystemZISD::SDIVREM, Op0, Op1, Ops[1], Ops[0]);
5131 case ISD::SDIVREM:
5321 OPCODE(SDIVREM);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 86 setOperationAction(ISD::SDIVREM, VT, Expand);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 236 case ISD::SDIVREM: return "sdivrem";
|
| H A D | LegalizeDAG.cpp | 2182 bool isSigned = Opcode == ISD::SDIVREM;
3280 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3299 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
4172 case ISD::SDIVREM:
|
| H A D | LegalizeIntegerTypes.cpp | 3300 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3301 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3491 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3492 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
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| H A D | LegalizeVectorOps.cpp | 375 case ISD::SDIVREM:
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| H A D | TargetLowering.cpp | 7361 // FIXME: Ideally we would always produce an SDIVREM here, but if the
7362 // type isn't legal, SDIVREM cannot be expanded. There is no reason why
7365 isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
7366 Quot = DAG.getNode(ISD::SDIVREM, dl,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 198 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
205 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
238 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
285 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
459 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
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| H A D | MipsISelLowering.cpp | 498 setTargetDAGCombine(ISD::SDIVREM);
575 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
1161 case ISD::SDIVREM:
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 137 setOperationAction(ISD::SDIVREM, MVT::i8, Promote);
143 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 981 case ISD::SDIVREM:
|
| H A D | ARMISelLowering.cpp | 1188 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1190 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1193 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
9372 case ISD::SDIVREM:
9443 case ISD::SDIVREM:
16193 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
16196 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
16211 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
16214 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
16238 assert((Opcode == ISD::SDIVREM || Opcod
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 108 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 314 setOperationAction(ISD::SDIVREM, VT, Custom);
384 setOperationAction(ISD::SDIVREM, VT, Custom);
1134 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
1987 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
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| H A D | R600ISelLowering.cpp | 679 case ISD::SDIVREM: {
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 114 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1429 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1475 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1497 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1504 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4860 case ISD::SDIVREM:
4866 bool isSigned = Opcode == ISD::SDIVREM;
|
| H A D | X86TargetTransformInfo.cpp | 3477 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 142 setOperationAction(ISD::SDIVREM, XLenVT, Expand);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 359 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
360 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
362 setOperationAction(ISD::SDIVREM, VT, Expand);
|