Searched refs:RegVT (Results 1 - 18 of 18) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp247 for (MVT RegVT : RegParmTypes) {
249 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn);
251 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
254 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSwitchLoweringUtils.h208 MVT RegVT; member in struct:llvm::SwitchCG::BitTestBlock
222 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp229 EVT RegVT = VA.getLocVT(); local
230 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy;
234 << RegVT.getEVTString() << '\n';
242 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
247 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1070 EVT RegVT = VA.getLocVT(); local
1072 if (RegVT == MVT::i8) {
1074 } else if (RegVT == MVT::i16) {
1081 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1098 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1103 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1199 EVT RegVT = VA.getLocVT(); local
1209 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1212 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1215 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Ar
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp485 EVT RegVT = VA.getLocVT(); local
486 switch (RegVT.getSimpleVT().SimpleTy) {
489 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n");
495 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp460 EVT RegVT = VA.getLocVT(); local
461 switch (RegVT.getSimpleVT().SimpleTy) {
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
485 << RegVT.getEVTString() << "\n");
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp643 EVT RegVT = VA.getLocVT(); local
644 switch (RegVT.getSimpleVT().SimpleTy) {
649 << RegVT.getEVTString() << "\n";
656 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp788 MVT RegVT = VA.getLocVT(); local
790 RegVT = VA.getValVT();
792 const TargetRegisterClass *RC = getRegClassFor(RegVT);
794 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
800 assert(RegVT.getSizeInBits() <= 32);
801 SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
802 Copy, DAG.getConstant(1, dl, RegVT));
803 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
807 unsigned RegSize = RegVT.getSizeInBits();
809 Subtarget.isHVXVectorType(RegVT));
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1302 EVT RegVT = VA.getLocVT(); local
1303 switch (RegVT.getSimpleVT().SimpleTy) {
1308 << RegVT.getEVTString() << "\n";
1315 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp6613 EVT RegVT = Value.getValueType();
6614 EVT RegSclVT = RegVT.getScalarType();
6711 MVT RegVT = getRegisterType(*DAG.getContext(), intVT);
6713 unsigned RegBytes = RegVT.getSizeInBits() / 8;
6717 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
6733 RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset),
6751 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
6861 MVT RegVT = getRegisterType(
6866 unsigned RegBytes = RegVT.getSizeInBits() / 8;
6870 SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT);
[all...]
H A DSelectionDAGBuilder.cpp2679 B.RegVT = VT.getSimpleVT();
2680 B.Reg = FuncInfo.CreateReg(B.RegVT);
2718 MVT VT = BB.RegVT;
7970 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); local
7986 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
7992 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand);
7993 OpInfo.ConstraintVT = RegVT;
7997 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
8014 ValueVT = RegVT;
8043 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueV
8318 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); local
9818 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); local
[all...]
H A DLegalizeIntegerTypes.cpp1202 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); local
1204 // The argument is passed as NumRegs registers of type RegVT.
1208 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
1224 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp3650 MVT RegVT = VA.getLocVT();
3652 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3657 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3663 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3664 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3665 (RegVT == MVT::f64 && ValVT == MVT::i64))
3667 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3671 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp639 EVT RegVT = ST->getValue().getValueType(); local
646 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS;
650 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS;
654 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS;
682 EVT RegVT = LD->getValueType(0); local
688 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS;
692 Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS;
696 Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS;
H A DPPCISelLowering.cpp5319 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; local
5323 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5329 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5331 DAG.getLoad(RegVT, dl, LDChain, AddTOC,
5336 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5338 DAG.getLoad(RegVT, dl, LDChain, AddPtr,
5371 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; local
5392 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5395 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5402 RegVT));
6919 MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; local
6946 MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3400 EVT RegVT = VA.getLocVT(); local
3403 if (RegVT == MVT::i32)
3405 else if (RegVT == MVT::i64)
3407 else if (RegVT == MVT::f16)
3409 else if (RegVT == MVT::f32)
3411 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
3413 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
3415 else if (RegVT
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3400 EVT RegVT = VA.getLocVT();
3412 if (RegVT == MVT::i8)
3414 else if (RegVT == MVT::i16)
3416 else if (RegVT == MVT::i32)
3418 else if (Is64Bit && RegVT == MVT::i64)
3420 else if (RegVT == MVT::f32)
3422 else if (RegVT == MVT::f64)
3424 else if (RegVT == MVT::f80)
3426 else if (RegVT == MVT::f128)
3428 else if (RegVT
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp2677 EVT RegVT = VA.getLocVT(); local
2691 if (RegVT == MVT::v2f64) {
4056 EVT RegVT = VA.getLocVT(); local
4089 if (RegVT == MVT::f16)
4091 else if (RegVT == MVT::f32)
4093 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
4095 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
4097 else if (RegVT
[all...]

Completed in 438 milliseconds