/freebsd-11-stable/sys/cddl/boot/zfs/ |
H A D | sha256.c | 49 #define ROTR(x, n) (((x) >> (n)) | ((x) << ((sizeof (x) * NBBY)-(n)))) macro 52 #define BIGSIGMA0_256(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22)) 53 #define BIGSIGMA1_256(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25)) 54 #define SIGMA0_256(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ ((x) >> 3)) 55 #define SIGMA1_256(x) (ROTR( [all...] |
/freebsd-11-stable/sys/crypto/sha2/ |
H A D | sha256c.c | 105 #define ROTR(x, n) ((x >> n) | (x << (32 - n))) macro 106 #define S0(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22)) 107 #define S1(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25)) 108 #define s0(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHR(x, 3)) 109 #define s1(x) (ROTR( [all...] |
H A D | sha512c.c | 132 #define ROTR(x, n) ((x >> n) | (x << (64 - n))) macro 133 #define S0(x) (ROTR(x, 28) ^ ROTR(x, 34) ^ ROTR(x, 39)) 134 #define S1(x) (ROTR(x, 14) ^ ROTR(x, 18) ^ ROTR(x, 41)) 135 #define s0(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHR(x, 7)) 136 #define s1(x) (ROTR( [all...] |
/freebsd-11-stable/crypto/openssh/ |
H A D | blocks.c | 41 #define ROTR(x,c) (((x) >> (c)) | ((x) << (64 - (c)))) macro 45 #define Sigma0(x) (ROTR(x,28) ^ ROTR(x,34) ^ ROTR(x,39)) 46 #define Sigma1(x) (ROTR(x,14) ^ ROTR(x,18) ^ ROTR(x,41)) 47 #define sigma0(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHR(x,7)) 48 #define sigma1(x) (ROTR( [all...] |
/freebsd-11-stable/crypto/openssl/crypto/sha/asm/ |
H A D | sha512-mips.pl | 90 $ROTR="drotr"; 105 $ROTR="rotr"; 176 $ROTR $tmp0,$e,@Sigma1[0] 178 $ROTR $tmp1,$e,@Sigma1[1] 180 $ROTR $h,$e,@Sigma1[2] 182 $ROTR $tmp1,$a,@Sigma0[0] 186 $ROTR $h,$a,@Sigma0[1] 190 $ROTR $tmp1,$a,@Sigma0[2] 249 $ROTR $tmp0,@X[1],@sigma0[1] 252 $ROTR [all...] |
H A D | sha512-ia64.pl | 441 _rotr r10=$t1,$Sigma1[0] } // ROTR(e,14) 447 _rotr r11=$t1,$Sigma1[1] } // ROTR(e,41) 474 _rotr r10=$t1,$Sigma1[0] } // ROTR(e,14) 476 _rotr r11=$t1,$Sigma1[1] };; // ROTR(e,18) 481 _rotr r11=$t1,$Sigma1[2] } // ROTR(e,41) 486 _rotr r8=$t0,$Sigma0[0] } // ROTR(a,28) 488 _rotr r9=$t0,$Sigma0[1] };; // ROTR(a,34) 491 _rotr r9=$t0,$Sigma0[2] };; // ROTR(a,39) 509 _rotr r8=X[15-1],$sigma0[0] } // ROTR(s0,1) 513 _rotr r9=X[15-1],$sigma0[1] } // ROTR(s [all...] |
H A D | sha512-armv4.pl | 92 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) 147 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) 326 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7)) 343 @ sigma1(x) (ROTR((x),19) ^ ROTR(( [all...] |
/freebsd-11-stable/crypto/openssl/crypto/sha/ |
H A D | sha512.c | 323 # define ROTR(a,n) ({ SHA_LONG64 ret; \ macro 353 # define ROTR(a,n) ({ SHA_LONG64 ret; \ macro 358 # define ROTR(a,n) ({ SHA_LONG64 ret; \ macro 373 # define ROTR(a,n) _rotr64((a),n) macro 402 # ifndef ROTR 403 # define ROTR(x,s) (((x)>>s) | (x)<<(64-s)) macro 405 # define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) 406 # define Sigma1(x) (ROTR(( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 29 case ISD::ROTR: return ARM_AM::ror; 30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
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/freebsd-11-stable/secure/lib/libcrypto/arm/ |
H A D | sha512-armv4.S | 137 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)) 192 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39)) 231 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7)) 248 @ sigma1(x) (ROTR((x),19) ^ ROTR(( [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 2300 { ISD::ROTR, MVT::v8i64, 1 }, 2301 { ISD::ROTR, MVT::v4i64, 1 }, 2302 { ISD::ROTR, MVT::v2i64, 1 }, 2303 { ISD::ROTR, MVT::v16i32, 1 }, 2304 { ISD::ROTR, MVT::v8i32, 1 }, 2305 { ISD::ROTR, MVT::v4i32, 1 } 2307 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2317 { ISD::ROTR, MVT::v4i64, 6 }, 2318 { ISD::ROTR, MVT::v8i32, 6 }, 2319 { ISD::ROTR, MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16ISelLowering.cpp | 144 setOperationAction(ISD::ROTR, MVT::i32, Expand); 145 setOperationAction(ISD::ROTR, MVT::i64, Expand);
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H A D | MipsFastISel.cpp | 1629 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 93 setOperationAction(ISD::ROTR, MVT::i8, Custom); 94 setOperationAction(ISD::ROTR, MVT::i16, Expand); 300 case ISD::ROTR: 319 case ISD::ROTR: 691 case ISD::ROTR:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 94 setOperationAction(ISD::ROTR, VT, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 104 setOperationAction(ISD::ROTR, MVT::i32, Legal);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 245 case ISD::ROTR: return "rotr";
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H A D | LegalizeVectorOps.cpp | 391 case ISD::ROTR: 921 case ISD::ROTR:
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H A D | TargetLowering.cpp | 2569 case ISD::ROTR: { 5160 // We need ROTR to do this. 5161 if (!isOperationLegalOrCustom(ISD::ROTR, VT)) 5166 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags); 5412 // We need ROTR to do this. 5413 if (!isOperationLegalOrCustom(ISD::ROTR, VT)) 5418 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags); 5998 unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 83 setOperationAction(ISD::ROTR, MVT::i8, Expand); 85 setOperationAction(ISD::ROTR, MVT::i16, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1429 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, 1478 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR, 1617 setOperationAction(ISD::ROTR, MVT::i32, Legal); 1618 setOperationAction(ISD::ROTR, MVT::i64, Legal);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 421 // TODO: we may consider expanding ROTL/ROTR on older GPUs. Currently on GPUs 425 setOperationAction(ISD::ROTR, MVT::i64, Legal); 427 setOperationAction(ISD::ROTR, MVT::i32, Legal); 430 setOperationAction(ISD::ROTR, MVT::i16, Expand); 432 setOperationAction(ISD::ROTR, MVT::i8, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 405 case ISD::ROTR: 2562 case ISD::ROTR: 3082 case ISD::ROTR:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 119 setOperationAction(ISD::ROTR, MVT::i32, Expand);
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