Searched refs:RD4 (Results 1 - 25 of 63) sorted by relevance

123

/freebsd-11-stable/sys/arm/at91/
H A Dat91_pit.c73 RD4(struct pit_softc *sc, bus_size_t off) function
96 last = PIT_PIV(RD4(sc, PIT_PIIR));
104 piv = PIT_PIV(RD4(sc, PIT_PIIR));
179 if (RD4(sc, PIT_SR) & PIT_PITS_DONE) {
180 icnt = RD4(sc, PIT_PIVR) >> 20;
183 timecount += PIT_PIV(RD4(sc, PIT_MR)) * icnt;
196 piir = RD4(sc, PIT_PIIR); /* Current count | over flows */
198 return (timecount + PIT_PIV(piir) + PIT_PIV(RD4(sc, PIT_MR)) * icnt);
H A Dat91_rtc.c81 RD4(struct at91_rtc_softc *sc, bus_size_t off) function
122 status = RD4(sc, RTC_SR);
178 if (RTC_CALR_CEN(RD4(sc, RTC_CALR)) == 19)
266 if (RD4(sc, RTC_VER) & (RTC_VER_NVTIM | RTC_VER_NVCAL))
276 timr = RD4(sc, RTC_TIMR);
277 calr = RD4(sc, RTC_CALR);
278 timr2 = RD4(sc, RTC_TIMR);
279 calr2 = RD4(sc, RTC_CALR);
310 while ((RD4(sc, RTC_SR) & RTC_SR_SECEV) == 0)
319 while ((RD4(s
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H A Dif_ate.c167 RD4(struct ate_softc *sc, bus_size_t off) function
295 (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII;
298 (RD4(sc, ETHB_UIO) & ETHB_UIO_RMII) == ETHB_UIO_RMII;
674 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE);
740 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE);
785 reg = RD4(sc, ETH_CFG);
829 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE);
830 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE);
831 c = RD4(sc, ETH_SCOL);
834 c = RD4(s
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H A Dat91_pio.c77 RD4(struct at91_pio_softc *sc, bus_size_t off) function
178 RD4(sc, PIO_ABSR), RD4(sc, PIO_OSR), RD4(sc, PIO_PSR),
179 RD4(sc, PIO_ODSR));
263 status = RD4(sc, PIO_ISR) & RD4(sc, PIO_IMR);
417 *(uint32_t *)data = RD4(sc, PIO_PDSR);
473 info->output_status = RD4(sc, PIO_ODSR);
474 info->input_status = RD4(s
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H A Dat91_rst.c68 RD4(struct at91_rst_softc *sc, bus_size_t off) function
156 switch (RD4(sc, RST_SR) & RST_SR_RST_MASK) {
191 } else if ((RD4(sc, RST_SR) & RST_SR_NRSTL)) {
206 if (RD4(sc, RST_SR) & RST_SR_URSTS) {
/freebsd-11-stable/sys/arm/freescale/imx/
H A Dimx6_snvs.c82 RD4(struct snvs_softc *sc, bus_size_t offset) function
108 while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit)
121 if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) {
133 counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32);
134 counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
135 counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32);
136 counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB);
H A Dimx6_ccm.c66 RD4(struct ccm_softc *sc, bus_size_t off) function
177 reg = RD4(sc, CCM_CGPR);
180 reg = RD4(sc, CCM_CLPCR);
224 reg = RD4(sc, CCM_CSCMR1);
239 reg = RD4(sc, CCM_CS1CDR);
253 reg = RD4(sc, CCM_CS2CDR);
271 WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS);
325 WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA);
328 v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET);
333 if (RD4(ccm_s
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H A Dimx6_src.c59 RD4(struct src_softc *sc, bus_size_t off) function
81 reg = RD4(src_sc, SRC_SCR);
86 reg = RD4(src_sc, SRC_SCR);
/freebsd-11-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c419 RD4(sc, sc->base_reg, &reg);
432 RD4(sc, sc->base_reg, &reg);
497 RD4(sc, sc->base_reg, &val);
523 RD4(sc, sc->misc_reg, &reg);
528 RD4(sc, sc->misc_reg, &reg);
533 RD4(sc, sc->base_reg, &reg);
572 RD4(sc, sc->base_reg, &reg);
576 RD4(sc, PLLE_AUX, &reg);
582 RD4(sc, sc->misc_reg, &reg);
592 RD4(s
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H A Dtegra124_pmc.c137 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
192 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);
199 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
212 reg = RD4(sc, PMC_PWRGATE_TOGGLE);
239 reg = RD4(sc, PMC_PWRGATE_STATUS);
252 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);
260 reg = RD4(sc, PMC_CLAMP_STATUS);
275 reg = RD4(sc, PMC_PWRGATE_STATUS);
514 reg = RD4(sc, PMC_CNTRL);
519 reg = RD4(s
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H A Dtegra124_xusbpadctl.c178 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
376 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
385 reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx));
397 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
402 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
407 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
421 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
426 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
433 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
439 reg = RD4(s
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H A Dtegra124_clk_super.c163 RD4(sc, sc->base_reg, &reg);
201 RD4(sc, sc->base_reg, &reg);
215 RD4(sc, sc->base_reg, &dummy);
219 RD4(sc, sc->base_reg, &dummy);
226 RD4(sc, sc->base_reg, &dummy);
/freebsd-11-stable/sys/dev/cadence/
H A Dif_cgem.c194 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
228 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i));
229 uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff;
310 net_cfg = RD4(sc, CGEM_NET_CFG);
834 sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT);
835 sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32;
837 sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX);
838 sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX);
839 sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX);
840 sc->stats.tx_frames_pause += RD4(s
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/freebsd-11-stable/sys/arm/xilinx/
H A Dzy7_slcr.c76 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
139 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
273 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
299 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
363 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
412 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
492 reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit));
509 reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN);
598 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
603 pss_idcode = RD4(s
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H A Dzy7_gpio.c98 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) macro
179 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) {
181 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0)
208 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31)));
212 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) &
216 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) |
221 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31)));
223 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31)));
262 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1;
279 RD4(s
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H A Duart_dev_cdnc.c57 #define RD4(bas, reg) \ macro
337 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
343 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
355 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
369 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
376 c = RD4(bas, CDNC_UART_FIFO);
497 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) &
519 status = RD4(bas, CDNC_UART_ISTAT_REG);
529 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
531 c = RD4(ba
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/freebsd-11-stable/sys/dev/sdhci/
H A Dfsl_sdhci.c186 RD4(struct fsl_sdhci_softc *sc, bus_size_t off) function
211 wrk32 = RD4(sc, SDHC_PROT_CTRL);
251 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
273 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37);
296 val32 = RD4(sc, SDHCI_INT_STATUS);
297 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
309 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
318 val32 = RD4(sc, off);
386 val32 = RD4(sc, SDHC_PROT_CTRL);
410 val32 = RD4(s
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/freebsd-11-stable/sys/dev/tpm/
H A Dtpm_crb.c191 crb_sc->rsp_off = RD4(sc, TPM_CRB_CTRL_RSP_ADDR);
192 crb_sc->rsp_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_RSP_HADDR) << 32);
194 crb_sc->cmd_off = RD4(sc, TPM_CRB_CTRL_CMD_LADDR);
195 crb_sc->cmd_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_CMD_HADDR) << 32);
196 crb_sc->cmd_buf_size = RD4(sc, TPM_CRB_CTRL_CMD_SIZE);
197 crb_sc->rsp_buf_size = RD4(sc, TPM_CRB_CTRL_RSP_SIZE);
252 if ((RD4(sc, off) & mask) == val)
256 if ((RD4(sc, off) & mask) == val)
324 if (RD4(sc, TPM_CRB_CTRL_STS) & TPM_CRB_CTRL_STS_ERR_BIT) {
338 if (!(RD4(s
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/freebsd-11-stable/sys/arm/nvidia/
H A Dtegra_efuse.c54 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_sc)->fuse_begin + (_r)) macro
190 sku->sku_id = RD4(sc, TEGRA124_FUSE_SKU_INFO);
191 sku->soc_iddq_value = RD4(sc, TEGRA124_FUSE_SOC_IDDQ);
192 sku->cpu_iddq_value = RD4(sc, TEGRA124_FUSE_CPU_IDDQ);
193 sku->gpu_iddq_value = RD4(sc, TEGRA124_FUSE_GPU_IDDQ);
194 sku->soc_speedo_value = RD4(sc, TEGRA124_FUSE_SOC_SPEEDO_0);
195 sku->cpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_0);
196 sku->gpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_2);
235 return (RD4(dev_sc, addr));
H A Dtegra_usbphy.c313 #define RD4(sc, offs) \ macro
325 if ((RD4(sc, reg) & mask) == val)
338 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC);
361 val = RD4(sc, IF_USB_SUSP_CTRL);
366 val = RD4(sc, UTMIP_TX_CFG0);
370 val = RD4(sc, UTMIP_HSRX_CFG0);
377 val = RD4(sc, UTMIP_HSRX_CFG1);
382 val = RD4(sc, UTMIP_DEBOUNCE_CFG0);
387 val = RD4(sc, UTMIP_MISC_CFG0);
392 val = RD4(s
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H A Dtegra_soctherm.c127 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
374 val = RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0);
393 val = RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0);
399 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0),
400 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1),
401 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2),
402 RD4(sc, sensor->sensor_base + TSENSOR_STATUS0),
403 RD4(sc, sensor->sensor_base + TSENSOR_STATUS1),
404 RD4(sc, sensor->sensor_base + TSENSOR_STATUS2)
432 val = RD4(s
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/freebsd-11-stable/sys/dev/extres/clk/
H A Dclk_mux.c45 #define RD4(_clk, off, val) \ macro
84 rv = RD4(clk, sc->offset, &reg);
110 RD4(clk, sc->offset, &reg);
/freebsd-11-stable/sys/arm/allwinner/
H A Daw_thermal.c115 #define RD4(sc, reg) bus_read_4((sc)->res, (reg)) macro
140 WR4(sc, THS_INTS, RD4(sc, THS_INTS));
143 WR4(sc, THS_FILTER, RD4(sc, THS_FILTER) | FILTER_EN);
167 val = aw_thermal_gettemp(RD4(sc, THS_DATA0 + (sensor * 4)));
H A Daw_sid.c90 #define RD4(sc, reg) bus_read_4((sc)->res, (reg)) macro
152 *calib0 = RD4(sc, SID_THERMAL_CALIB0);
153 *calib1 = RD4(sc, SID_THERMAL_CALIB1);
170 tmp = RD4(aw_sid_sc, aw_sid_sc->root_key_off + (i * 4));
/freebsd-11-stable/sys/dev/ffec/
H A Dif_ffec.c223 RD4(struct ffec_softc *sc, bus_size_t off) function
309 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
335 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
386 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
387 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
389 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
481 mibc = RD4(sc, FEC_MIBC_REG);
528 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS));
529 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT));
531 RD4(s
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