nvidia/tegra124/tegra124_xusbpadctl.c

178 #define	RD4(_sc, _r)		bus_read_4((_sc)->mem_res, (_r))
376 	reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
385 	reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx));
397 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
402 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
407 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
421 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
426 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
433 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
439 		reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
448 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
460 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
464 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
479 	reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
484 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
489 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
493 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
498 		reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
507 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
511 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
523 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
527 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
532 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
537 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
543 	reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
564 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
571 	reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);
576 	reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));
594 	reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));
613 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
632 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
653 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
658 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
663 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
676 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
681 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
686 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
858 	reg = RD4(sc, lane->reg);