Searched refs:MULHU (Results 1 - 25 of 30) sorted by relevance

12

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16ISelDAGToDAG.cpp211 case ISD::MULHU: {
212 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
H A DMipsSEISelLowering.cpp186 setOperationAction(ISD::MULHU, MVT::i32, Custom);
197 setOperationAction(ISD::MULHU, MVT::i64, Custom);
234 setOperationAction(ISD::MULHU, MVT::i32, Legal);
281 setOperationAction(ISD::MULHU, MVT::i64, Legal);
457 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h438 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
441 MULHU, MULHS, enumerator in enum:llvm::ISD::NodeType
H A DTargetLowering.h2244 case ISD::MULHU:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp93 setOperationAction(ISD::MULHU, T, Custom);
152 setOperationAction(ISD::MULHU, T, Custom);
1544 case ISD::MULHU:
1579 case ISD::MULHU: return LowerHvxMulh(Op, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp338 setOperationAction(ISD::MULHU, MVT::i64, Expand);
367 setOperationAction(ISD::MULHU, VT, Expand);
492 setTargetDAGCombine(ISD::MULHU);
1706 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1721 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1735 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
1875 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1887 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1900 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
3995 case ISD::MULHU
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h389 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
844 X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
1054 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
H A DX86ISelLowering.cpp303 setOperationAction(ISD::MULHU, VT, Expand);
791 setOperationAction(ISD::MULHU, VT, Expand);
891 setOperationAction(ISD::MULHU, MVT::v4i32, Custom);
893 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
895 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
1276 setOperationAction(ISD::MULHU, MVT::v8i32, Custom);
1278 setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom);
1280 setOperationAction(ISD::MULHU, MVT::v32i8, Custom);
1555 setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
1779 setOperationAction(ISD::MULHU, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp90 setOperationAction(ISD::MULHU, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp112 setOperationAction(ISD::MULHU, MVT::i32, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp228 case ISD::MULHU: return "mulhu";
H A DTargetLowering.cpp4902 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT)
4903 : isOperationLegalOrCustom(ISD::MULHU, VT))
4904 return DAG.getNode(ISD::MULHU, dl, VT, X, Y);
4926 // MULHU to act as a SRL-by-1 for NPQ, else multiply by zero.
5749 isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
5777 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
7236 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU;
7500 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
H A DLegalizeDAG.cpp3309 case ISD::MULHU:
3312 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3327 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3365 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
H A DLegalizeVectorOps.cpp370 case ISD::MULHU:
H A DLegalizeVectorTypes.cpp910 case ISD::MULHU:
2715 case ISD::MULHU:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp124 setOperationAction(ISD::MULHU, MVT::i8, Promote);
129 setOperationAction(ISD::MULHU, MVT::i16, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp534 if (TLI->isOperationLegalOrCustom(ISD::MULHU, VT)) {
H A DAArch64ISelLowering.cpp810 setOperationAction(ISD::MULHU, VT, Legal);
813 setOperationAction(ISD::MULHU, VT, Expand);
2299 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
H A DAArch64FastISel.cpp3810 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp114 setOperationAction(ISD::MULHU, MVT::i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp176 setOperationAction(ISD::MULHU, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp113 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp101 setOperationAction(ISD::MULHU, MVT::i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1648 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1671 setOperationAction(ISD::MULHU, MVT::i64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp128 setOperationAction(ISD::MULHU, XLenVT, Expand);

Completed in 685 milliseconds

12