Searched refs:INSERT_VECTOR_ELT (Results 1 - 25 of 27) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h383 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
386 INSERT_VECTOR_ELT, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp802 if (ISD == ISD::INSERT_VECTOR_ELT)
835 if (ISD == ISD::INSERT_VECTOR_ELT)
843 ISD == ISD::INSERT_VECTOR_ELT)
H A DPPCISelLowering.cpp675 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
919 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
974 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
975 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1007 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
1055 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
1096 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
9966 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT &&
9967 "Should only be called for ISD::INSERT_VECTOR_ELT");
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp214 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
215 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
216 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
217 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
281 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
481 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
737 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
1887 case ISD::INSERT_VECTOR_ELT: {
H A DSIISelLowering.cpp271 case ISD::INSERT_VECTOR_ELT:
300 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
301 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);
318 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);
319 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
320 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
328 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
329 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
330 setOperationAction(ISD::INSERT_VECTOR_ELT, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp430 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx);
434 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
H A DLegalizeVectorTypes.cpp56 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
837 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
1417 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
1421 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
2692 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2928 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
3683 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
4731 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem,
4860 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
H A DSelectionDAGDumper.cpp280 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
H A DLegalizeDAG.cpp120 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
359 /// INSERT_VECTOR_ELT instruction. In this case, it
3028 case ISD::INSERT_VECTOR_ELT:
4226 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4610 case ISD::INSERT_VECTOR_ELT: {
4653 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
H A DLegalizeIntegerTypes.cpp99 case ISD::INSERT_VECTOR_ELT:
1272 case ISD::INSERT_VECTOR_ELT:
3775 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
4397 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
H A DTargetLowering.cpp750 case ISD::INSERT_VECTOR_ELT: {
883 case ISD::INSERT_VECTOR_ELT: {
2376 case ISD::INSERT_VECTOR_ELT: {
H A DDAGCombiner.cpp1605 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
16729 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT &&
16897 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
16902 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT,
16905 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
17075 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT &&
19100 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT)
19119 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Shuf), Op0.getValueType(),
H A DSelectionDAG.cpp3266 case ISD::INSERT_VECTOR_ELT: {
3855 case ISD::INSERT_VECTOR_ELT: {
5357 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
5359 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
5595 case ISD::INSERT_VECTOR_ELT: {
5597 // INSERT_VECTOR_ELT into out-of-bounds element is an UNDEF
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp98 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
189 setOperationAction(ISD::INSERT_VECTOR_ELT, BoolV, Custom);
1566 case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG);
H A DHexagonISelLowering.cpp1491 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1539 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
2905 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp155 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) {
1018 case ISD::INSERT_VECTOR_ELT:
1463 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp354 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
491 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
492 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
4882 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
4954 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
4984 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
5193 case ISD::INSERT_VECTOR_ELT:
6109 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) {
6134 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VecVT,
H A DSystemZISelDAGToDAG.cpp1576 case ISD::INSERT_VECTOR_ELT: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp169 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
259 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
321 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
368 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
413 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
941 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
2003 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2017 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
4077 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, d
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp329 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
383 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
1963 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
2458 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2516 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2526 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp660 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
893 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
3217 case ISD::INSERT_VECTOR_ELT:
7367 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
8083 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
8102 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
8111 "of INSERT_VECTOR_ELT\n");
8139 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
8152 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
8177 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, D
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp779 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
924 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
955 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1118 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1347 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1433 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1615 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1745 setOperationAction(ISD::INSERT_VECTOR_ELT, V
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1642 case InsertElement: return ISD::INSERT_VECTOR_ELT;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp995 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
1001 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp390 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Expand);

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