/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 383 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 386 INSERT_VECTOR_ELT, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 802 if (ISD == ISD::INSERT_VECTOR_ELT) 835 if (ISD == ISD::INSERT_VECTOR_ELT) 843 ISD == ISD::INSERT_VECTOR_ELT)
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H A D | PPCISelLowering.cpp | 675 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 919 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 974 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 975 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 1007 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand); 1055 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand); 1096 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand); 9966 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && 9967 "Should only be called for ISD::INSERT_VECTOR_ELT"); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 214 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); 215 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); 216 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 217 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 281 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 481 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 737 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), 1887 case ISD::INSERT_VECTOR_ELT: {
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H A D | SIISelLowering.cpp | 271 case ISD::INSERT_VECTOR_ELT: 300 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); 301 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); 317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom); 318 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom); 319 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 320 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom); 328 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom); 329 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom); 330 setOperationAction(ISD::INSERT_VECTOR_ELT, MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypesGeneric.cpp | 430 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); 434 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
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H A D | LegalizeVectorTypes.cpp | 56 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 837 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 1417 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 1421 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 2692 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 2928 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx], 3683 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), 4731 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, 4860 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
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H A D | SelectionDAGDumper.cpp | 280 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
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H A D | LegalizeDAG.cpp | 120 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 359 /// INSERT_VECTOR_ELT instruction. In this case, it 3028 case ISD::INSERT_VECTOR_ELT: 4226 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) { 4610 case ISD::INSERT_VECTOR_ELT: { 4653 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
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H A D | LegalizeIntegerTypes.cpp | 99 case ISD::INSERT_VECTOR_ELT: 1272 case ISD::INSERT_VECTOR_ELT: 3775 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 4397 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
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H A D | TargetLowering.cpp | 750 case ISD::INSERT_VECTOR_ELT: { 883 case ISD::INSERT_VECTOR_ELT: { 2376 case ISD::INSERT_VECTOR_ELT: {
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H A D | DAGCombiner.cpp | 1605 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 16729 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT && 16897 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() 16902 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, 16905 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), 17075 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT && 19100 if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT) 19119 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Shuf), Op0.getValueType(),
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H A D | SelectionDAG.cpp | 3266 case ISD::INSERT_VECTOR_ELT: { 3855 case ISD::INSERT_VECTOR_ELT: { 5357 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 5359 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 5595 case ISD::INSERT_VECTOR_ELT: { 5597 // INSERT_VECTOR_ELT into out-of-bounds element is an UNDEF
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 98 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); 189 setOperationAction(ISD::INSERT_VECTOR_ELT, BoolV, Custom); 1566 case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG);
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H A D | HexagonISelLowering.cpp | 1491 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, 1539 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom); 2905 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 155 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) { 1018 case ISD::INSERT_VECTOR_ELT: 1463 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 354 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); 491 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 492 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 4882 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], 4954 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, 4984 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT, 5193 case ISD::INSERT_VECTOR_ELT: 6109 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) { 6134 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VecVT,
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H A D | SystemZISelDAGToDAG.cpp | 1576 case ISD::INSERT_VECTOR_ELT: {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 169 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 259 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 321 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom); 368 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 413 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 941 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 2003 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 2017 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 4077 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, d [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 329 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 383 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 1963 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 2458 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT. 2516 // Use INSERT_VECTOR_ELT operations rather than expand to stores. 2526 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 660 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 893 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 3217 case ISD::INSERT_VECTOR_ELT: 7367 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, 8083 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); 8102 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we 8111 "of INSERT_VECTOR_ELT\n"); 8139 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); 8152 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); 8177 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, D [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 779 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 924 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 955 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 1118 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 1347 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 1433 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 1615 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 1745 setOperationAction(ISD::INSERT_VECTOR_ELT, V [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1642 case InsertElement: return ISD::INSERT_VECTOR_ELT;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 995 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo, 1001 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 390 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Expand);
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