Searched refs:FREM (Results 1 - 25 of 28) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h295 FADD, FSUB, FMUL, FDIV, FREM, enumerator in enum:llvm::ISD::NodeType
H A DTargetLowering.h2287 case ISD::FREM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h702 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
H A DSelectionDAGDumper.cpp259 case ISD::FREM: return "frem";
H A DLegalizeFloatTypes.cpp111 case ISD::FREM: R = SoftenFloatRes_FREM(N); break;
1185 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break;
2134 case ISD::FREM:
H A DLegalizeVectorTypes.cpp131 case ISD::FREM:
930 case ISD::FREM:
2739 case ISD::FREM:
H A DLegalizeVectorOps.cpp381 case ISD::FREM:
H A DFastISel.cpp1838 return selectBinaryOp(I, ISD::FREM);
H A DLegalizeDAG.cpp4106 case ISD::FREM:
4450 case ISD::FREM:
H A DSelectionDAG.cpp4097 case ISD::FREM:
5090 case ISD::FREM:
5114 case ISD::FREM:
5212 case ISD::FREM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp417 case ISD::FREM:
H A DAMDGPUISelLowering.cpp272 setOperationAction(ISD::FREM, MVT::f32, Custom);
273 setOperationAction(ISD::FREM, MVT::f64, Custom);
413 setOperationAction(ISD::FREM, VT, Expand);
560 case ISD::FREM:
1135 case ISD::FREM: return LowerFREM(Op, DAG);
H A DSIISelLowering.cpp8596 case ISD::FREM:
8770 case ISD::FREM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1619 setOperationAction(ISD::FREM , MVT::f128, Expand);
1624 setOperationAction(ISD::FREM , MVT::f64, Expand);
1629 setOperationAction(ISD::FREM , MVT::f32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp245 setOperationAction(ISD::FREM, MVT::f32, Expand);
246 setOperationAction(ISD::FREM, MVT::f64, Expand);
247 setOperationAction(ISD::FREM, MVT::f80, Expand);
267 setOperationAction(ISD::FREM, MVT::f128, Expand);
399 setOperationAction(ISD::FREM, MVT::f16, Promote);
400 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
401 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
717 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
918 setOperationAction(ISD::FREM, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1606 case FRem: return ISD::FREM;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp94 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1482 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp259 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
293 setOperationAction(ISD::FREM , MVT::f64, Expand);
298 setOperationAction(ISD::FREM , MVT::f32, Expand);
658 setOperationAction(ISD::FREM, VT, Expand);
964 setOperationAction(ISD::FREM, MVT::f128, Expand);
991 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
1042 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp448 setOperationAction(ISD::FREM, MVT::f32, Expand);
449 setOperationAction(ISD::FREM, MVT::f64, Expand);
H A DMipsSEISelLowering.cpp136 setOperationAction(ISD::FREM, MVT::f16, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp164 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp212 setOperationAction(ISD::FREM, VT, Expand);
347 setOperationAction(ISD::FREM, VT, Expand);
783 // FIXME: Code duplication: FDIV and FREM are expanded always, see
786 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
958 setOperationAction(ISD::FREM, MVT::f64, Expand);
1330 setOperationAction(ISD::FREM, MVT::f64, Expand);
1331 setOperationAction(ISD::FREM, MVT::f32, Expand);
1406 setOperationAction(ISD::FREM, MVT::f16, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp572 for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,
585 // No FPOW or FREM in PTX.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp323 setOperationAction(ISD::FREM , MVT::f32 , Expand);
324 setOperationAction(ISD::FREM , MVT::f64 , Expand);
325 setOperationAction(ISD::FREM , MVT::f80 , Expand);
326 setOperationAction(ISD::FREM , MVT::f128 , Expand);
760 setOperationAction(ISD::FREM, VT, Expand);
1975 ISD::FREM, ISD::STRICT_FREM,
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