Searched refs:FDIV (Results 1 - 25 of 29) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp186 { ISD::FDIV, MVT::f32, 18 }, // divss
187 { ISD::FDIV, MVT::v4f32, 35 }, // divps
188 { ISD::FDIV, MVT::f64, 33 }, // divsd
189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd
204 { ISD::FDIV, MVT::f32, 17 }, // divss
205 { ISD::FDIV, MVT::v4f32, 39 }, // divps
206 { ISD::FDIV, MVT::f64, 32 }, // divsd
207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd
702 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/
703 { ISD::FDIV, MV
[all...]
H A DX86IntrinsicsInfo.h449 X86_INTRINSIC_DATA(avx512_div_pd_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
450 X86_INTRINSIC_DATA(avx512_div_ps_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h295 FADD, FSUB, FMUL, FDIV, FREM, enumerator in enum:llvm::ISD::NodeType
H A DTargetLowering.h2286 case ISD::FDIV:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h705 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
H A DSelectionDAGDumper.cpp254 case ISD::FDIV: return "fdiv";
H A DLegalizeFloatTypes.cpp81 case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break;
1143 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break;
2127 case ISD::FDIV:
H A DLegalizeVectorTypes.cpp112 case ISD::FDIV:
920 case ISD::FDIV:
2738 case ISD::FDIV:
H A DLegalizeVectorOps.cpp380 case ISD::FDIV:
H A DFastISel.cpp1832 return selectBinaryOp(I, ISD::FDIV);
H A DSelectionDAG.cpp4096 case ISD::FDIV:
5087 case ISD::FDIV:
5113 case ISD::FDIV:
5211 case ISD::FDIV:
7309 if (Opcode == ISD::FMUL || Opcode == ISD::FDIV)
H A DTargetLowering.cpp2550 case ISD::FDIV:
5564 case ISD::FDIV:
5671 case ISD::FDIV:
H A DLegalizeDAG.cpp4100 case ISD::FDIV:
4449 case ISD::FDIV:
H A DDAGCombiner.cpp1581 case ISD::FDIV: return visitFDIV(N);
12665 // may have different costs for FDIV and FMUL, so sometimes the cost of two
12666 // FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason
12667 // is the critical path is increased from "one FDIV" to "one FDIV + one FMUL".
12698 // Find all FDIV users of the same divisor.
12702 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) {
12717 SDValue Reciprocal = DAG.getNode(ISD::FDIV, DL, VT, FPOne, N1, Flags);
12752 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1, Flags);
12780 // If this FDIV i
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp416 case ISD::FDIV:
H A DAMDGPUISelLowering.cpp409 setOperationAction(ISD::FDIV, VT, Expand);
559 case ISD::FDIV:
2032 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
H A DSIISelLowering.cpp443 setOperationAction(ISD::FDIV, MVT::f32, Custom);
444 setOperationAction(ISD::FDIV, MVT::f64, Custom);
518 setOperationAction(ISD::FDIV, MVT::f16, Custom);
4052 case ISD::FDIV: return LowerFDIV(Op, DAG);
8595 case ISD::FDIV:
8769 case ISD::FDIV:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1714 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1739 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1791 setOperationAction(ISD::FDIV, MVT::f32, Promote);
3044 case ISD::FDIV: return LowerF128Op(Op, DAG,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp135 setOperationAction(ISD::FDIV, MVT::f16, Promote);
389 setOperationAction(ISD::FDIV, Ty, Legal);
1868 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp262 setOperationAction(ISD::FDIV, MVT::f128, Custom);
441 setOperationAction(ISD::FDIV, MVT::f16, Promote);
461 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
465 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
487 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
640 setTargetDAGCombine(ISD::FDIV);
710 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
3202 case ISD::FDIV:
12565 case ISD::FDIV:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp657 setOperationAction(ISD::FDIV, VT, Expand);
758 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
824 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
932 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1126 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1129 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
1132 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
1135 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
1202 setTargetDAGCombine(ISD::FDIV);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1603 case FDiv: return ISD::FDIV;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp208 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1481 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp209 setOperationAction(ISD::FDIV, VT, Expand);
346 setOperationAction(ISD::FDIV, VT, Expand);
783 // FIXME: Code duplication: FDIV and FREM are expanded always, see
785 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
924 setTargetDAGCombine(ISD::FDIV);
957 setOperationAction(ISD::FDIV, MVT::f64, Expand);
14648 case ISD::FDIV:

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