Searched refs:FADD (Results 1 - 25 of 32) sorted by relevance

12

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp208 { ISD::FADD, MVT::v2f64, 2 }, // addpd
543 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
547 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
695 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
696 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
752 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
753 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
754 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
755 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
837 { ISD::FADD, MV
[all...]
H A DX86IntrinsicsInfo.h418 X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
419 X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
H A DX86ISelLowering.cpp227 // 64-bit FILD followed by conditional FADD for other targets.
532 setOperationAction(ISD::FADD, VT, Custom);
688 setOperationAction(ISD::FADD, MVT::f128, LibCall);
1999 setTargetDAGCombine(ISD::FADD);
8872 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
9047 if (Opcode != ISD::FADD && Opcode != ISD::FSUB)
9091 // FADD is commutable. Try to commute the operands
9112 IsSubAdd = Opc[0] == ISD::FADD;
9241 case ISD::FADD: HOpcode = X86ISD::FHADD; break;
9279 if (GenericOpcode != ISD::ADD && GenericOpcode != ISD::FADD)
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h295 FADD, FSUB, FMUL, FDIV, FREM, enumerator in enum:llvm::ISD::NodeType
H A DTargetLowering.h655 /// takes more cycles to execute than FADD.
2248 case ISD::FADD:
2528 /// Returns true if the FADD or FSUB node passed could legally be combined with
2532 assert(N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB);
H A DBasicTTIImpl.h405 // Check whether FADD is available, as a proxy for floating-point in
409 if (TLI->isOperationLegalOrCustomOrPromote(ISD::FADD, VT))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp4999 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5002 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5015 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5018 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5021 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
5036 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
5039 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
5042 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
5045 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
5048 SDValue t11 = DAG.getNode(ISD::FADD, d
[all...]
H A DSelectionDAGBuilder.h695 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
H A DLegalizeVectorOps.cpp377 case ISD::FADD:
584 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
1405 DAG.getNode(ISD::FADD, DL, Node->getValueType(0), fHI, fLO));
1426 TLI.isOperationLegalOrCustom(ISD::FADD, VT))
H A DDAGCombiner.cpp1577 case ISD::FADD: return visitFADD(N);
11519 /// Try to perform FMA combining on a given FADD node.
11577 // Note: Commutes FADD operands.
11600 // Note: Commutes FADD operands.
12078 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) {
12149 return DAG.getNode(ISD::FADD, DL, VT, N0, N1, Flags);
12153 return DAG.getNode(ISD::FADD, DL, VT, N1, N0, Flags);
12188 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B, Flags);
12194 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B, Flags);
12220 if (N1CFP && N0.getOpcode() == ISD::FADD
[all...]
H A DSelectionDAGDumper.cpp248 case ISD::FADD: return "fadd";
H A DLegalizeFloatTypes.cpp73 case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
1135 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break;
1619 // TODO: Are there fast-math-flags to propagate to this FADD?
1620 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
2126 case ISD::FADD:
H A DTargetLowering.cpp2547 case ISD::FADD:
5540 case ISD::FADD:
5640 case ISD::FADD:
6216 !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
6261 Slow = DAG.getNode(ISD::FADD, dl, DstVT, SignCvt, SignCvt);
6274 !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
6307 Result = DAG.getNode(ISD::FADD, dl, DstVT, LoFlt, HiSub);
7615 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break;
H A DLegalizeDAG.cpp2483 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
3254 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3258 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
4118 case ISD::FADD:
4446 case ISD::FADD:
H A DLegalizeVectorTypes.cpp110 case ISD::FADD:
911 case ISD::FADD:
2070 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break;
2734 case ISD::FADD:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp406 setOperationAction(ISD::FADD, VT, Expand);
497 setTargetDAGCombine(ISD::FADD);
513 case ISD::FADD:
2061 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2140 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2194 return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
2288 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2501 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
3688 case ISD::FADD: {
3706 SDValue Res = DAG.getNode(ISD::FADD, S
[all...]
H A DAMDGPUTargetTransformInfo.cpp404 case ISD::FADD:
H A DSIISelLowering.cpp625 setOperationAction(ISD::FADD, MVT::v2f16, Legal);
652 setOperationAction(ISD::FADD, MVT::v4f16, Custom);
720 setTargetDAGCombine(ISD::FADD);
4099 case ISD::FADD:
8592 case ISD::FADD:
8761 case ISD::FADD:
9311 case ISD::FADD:
9671 if (LHS.getOpcode() == ISD::FADD) {
9683 if (RHS.getOpcode() == ISD::FADD) {
9714 if (LHS.getOpcode() == ISD::FADD) {
[all...]
H A DR600ISelLowering.cpp766 DAG.getNode(ISD::FADD, DL, VT,
782 DAG.getNode(ISD::FADD, DL, VT, FractPart,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp520 setTargetDAGCombine(ISD::FADD);
537 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
2116 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, A, PointFiveWithSign);
2147 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, AbsA,
4391 if (User->getOpcode() != ISD::FADD)
4762 case ISD::FADD:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1481 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1584 setOperationAction(ISD::FADD, MVT::f64, Expand);
1621 setOperationAction(ISD::FADD, MVT::f64, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp132 setOperationAction(ISD::FADD, MVT::f16, Promote);
388 setOperationAction(ISD::FADD, Ty, Legal);
1822 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1711 setOperationAction(ISD::FADD, MVT::f128, Legal);
1736 setOperationAction(ISD::FADD, MVT::f128, Custom);
3038 case ISD::FADD: return LowerF128Op(Op, DAG,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1812 case ISD::FADD:
2855 return SelectBinaryFPOp(I, ISD::FADD);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp259 setOperationAction(ISD::FADD, MVT::f128, Custom);
438 setOperationAction(ISD::FADD, MVT::f16, Promote);
458 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
462 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
484 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
706 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
3196 case ISD::FADD:

Completed in 826 milliseconds

12