/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 209 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); 210 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); 211 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 212 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 279 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 480 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), 575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), 577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), 579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, D [all...] |
H A D | SIISelLowering.cpp | 270 case ISD::EXTRACT_VECTOR_ELT: 297 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); 298 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32); 322 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom); 323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); 324 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom); 325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom); 326 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom); 332 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom); 333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MV [all...] |
H A D | AMDGPUISelLowering.cpp | 1338 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); 1339 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); 1349 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); 1357 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); 1390 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL, 2092 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); 2212 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One); 2347 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); 2348 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); 2488 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, S [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 297 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), 361 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, 387 ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op, 425 ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond, 527 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, 530 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, 586 case ISD::EXTRACT_VECTOR_ELT: 1336 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT, Operand, 1855 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input], 1928 case ISD::EXTRACT_VECTOR_ELT [all...] |
H A D | LegalizeTypesGeneric.cpp | 123 ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, CastInOp, 216 // The result of EXTRACT_VECTOR_ELT may be larger than the element type of 233 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); 237 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
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H A D | LegalizeDAG.cpp | 1004 case ISD::EXTRACT_VECTOR_ELT: 1292 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in 3007 case ISD::EXTRACT_VECTOR_ELT: 3094 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, 3098 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1, 3784 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0), 3787 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1), 4225 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT || 4566 case ISD::EXTRACT_VECTOR_ELT: { 4601 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, S [all...] |
H A D | LegalizeIntegerTypes.cpp | 68 case ISD::EXTRACT_VECTOR_ELT: 512 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1); 517 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1); 1271 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; 1811 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 4226 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 4341 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op, 4414 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 4417 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming 4451 ISD::EXTRACT_VECTOR_ELT, d [all...] |
H A D | LegalizeFloatTypes.cpp | 65 case ISD::EXTRACT_VECTOR_ELT: 228 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), 1125 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 2101 case ISD::EXTRACT_VECTOR_ELT: 2244 SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT,
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H A D | LegalizeVectorOps.cpp | 1515 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 1555 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, 1558 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
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H A D | SelectionDAGDumper.cpp | 281 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
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H A D | DAGCombiner.cpp | 340 /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed 343 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced. 1606 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 5249 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 10774 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 10778 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 10783 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 10802 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, TrTy, 10968 TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, VecSrcVT))) { 10973 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, S [all...] |
H A D | SelectionDAG.cpp | 2414 return getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(V), 3242 case ISD::EXTRACT_VECTOR_ELT: { 3892 case ISD::EXTRACT_VECTOR_ELT: { 4178 case ISD::EXTRACT_VECTOR_ELT: { 4263 if (Ops[i].getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4738 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 5317 case ISD::EXTRACT_VECTOR_ELT: 5319 "The result of EXTRACT_VECTOR_ELT must be at least as wide as the \ 5326 // EXTRACT_VECTOR_ELT of out-of-bounds element is an UNDEF 5330 // EXTRACT_VECTOR_ELT o [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 388 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 393 EXTRACT_VECTOR_ELT, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 100 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); 191 setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom); 426 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) 1076 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 1078 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NTy, 1568 case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 155 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) { 1017 case ISD::EXTRACT_VECTOR_ELT: 1279 if (Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 1299 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(), 1337 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 1344 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); 1901 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, 1949 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, 1951 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, 2187 case ISD::EXTRACT_VECTOR_ELT: 2375 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, 2377 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, 2385 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, 2600 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, 4886 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, D [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 353 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); 493 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 494 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 638 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1315 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value, 4482 // of an EXTRACT_VECTOR_ELT are smaller than the destination elements. Per 4683 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR 4691 // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still 4701 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5011 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, D [all...] |
H A D | SystemZISelDAGToDAG.cpp | 711 if (Index.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 1211 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 787 if (ISD == ISD::EXTRACT_VECTOR_ELT && 842 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
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H A D | PPCISelLowering.cpp | 674 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); 789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal); 796 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal); 797 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal); 798 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); 799 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 801 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); 1006 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal); 1054 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 778 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand); 848 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 944 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 956 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 1348 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 1379 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom); 1431 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 1618 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 1744 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 1786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 260 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 369 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 414 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 2194 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 2196 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 2826 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 2845 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 5548 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, d [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 328 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); 382 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); 465 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); 1783 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type 1784 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), 1798 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type 1799 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1803 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), 2190 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT becaus [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 244 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, 247 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, 861 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 864 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 892 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 3093 SDValue ExtractTrunc = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, 3219 case ISD::EXTRACT_VECTOR_ELT: 6575 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6708 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit 7368 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), 7903 // 5) if all operands are EXTRACT_VECTOR_ELT, check for VUZP. 7916 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) 7970 // Check that the type of EXTRACT_VECTOR_ELT matches the type of 8019 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT || [all...] |