Searched refs:CTLZ (Results 1 - 25 of 31) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1892 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
1896 { ISD::CTLZ, MVT::v8i64, 1 },
1897 { ISD::CTLZ, MVT::v16i32, 1 },
1898 { ISD::CTLZ, MVT::v32i16, 8 },
1899 { ISD::CTLZ, MVT::v64i8, 20 },
1900 { ISD::CTLZ, MVT::v4i64, 1 },
1901 { ISD::CTLZ, MVT::v8i32, 1 },
1902 { ISD::CTLZ, MVT::v16i16, 4 },
1903 { ISD::CTLZ, MVT::v32i8, 10 },
1904 { ISD::CTLZ, MV
[all...]
H A DX86ISelLowering.cpp347 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
796 setOperationAction(ISD::CTLZ, VT, Expand);
1057 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1058 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1059 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1060 setOperationAction(ISD::CTLZ, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp182 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, local
254 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True});
255 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True});
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h474 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp82 setOperationAction(ISD::CTLZ, T, Legal);
144 setOperationAction(ISD::CTLZ, T, Custom);
1240 // Lower vector CTTZ into a computation using CTLZ (Hacker's Delight):
1270 {VecW, DAG.getNode(ISD::CTLZ, dl, ResTy, A)});
1540 case ISD::CTLZ:
H A DHexagonISelLowering.cpp1406 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1407 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1479 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp113 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp398 case ISD::CTLZ: return "ctlz";
H A DTargetLowering.cpp3156 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
6445 isOperationLegalOrCustom(ISD::CTLZ, VT)) {
6446 Result = DAG.getNode(ISD::CTLZ, dl, VT, Op);
6454 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
6458 DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ);
6517 !isOperationLegalOrCustom(ISD::CTLZ, VT)) ||
6531 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6532 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) {
6535 DAG.getNode(ISD::CTLZ, dl, VT, Tmp));
7087 SDValue Clz = DAG.getNode(ISD::CTLZ, d
[all...]
H A DLegalizeVectorOps.cpp395 case ISD::CTLZ:
899 case ISD::CTLZ:
H A DLegalizeVectorTypes.cpp75 case ISD::CTLZ:
868 case ISD::CTLZ:
1966 case ISD::CTLZ:
2839 case ISD::CTLZ:
H A DLegalizeDAG.cpp2730 case ISD::CTLZ:
4240 case ISD::CTLZ:
4257 if (Node->getOpcode() == ISD::CTLZ ||
H A DLegalizeIntegerTypes.cpp64 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
1822 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
H A DDAGCombiner.cpp1556 case ISD::CTLZ: return visitCTLZ(N);
8035 if (N1C && N0.getOpcode() == ISD::CTLZ &&
8051 // could be set on input to the CTLZ node. If this bit is set, the SRL
8052 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
8247 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
20500 if ((Count.getOpcode() == ISD::CTLZ ||
20503 (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, VT)))
20504 return DAG.getNode(ISD::CTLZ, DL, VT, N0);
20587 SDValue Ctlz = DAG.getNode(ISD::CTLZ, DL, VT, V);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp107 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
108 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp323 setOperationAction(ISD::CTLZ, VT, Expand);
353 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
393 setOperationAction(ISD::CTLZ, VT, Expand);
1155 case ISD::CTLZ:
2315 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp127 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp273 setOperationAction(ISD::CTLZ, VT, Legal);
886 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
887 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
1102 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
3680 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
3700 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
3707 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
5974 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB); local
5975 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp181 setOperationAction(ISD::CTLZ, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp176 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp335 setOperationAction(ISD::CTLZ, Ty, Legal);
2085 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
H A DMipsISelLowering.cpp480 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
482 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1568 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1632 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp270 // We have native support for a 64-bit CTLZ, via FLOGR.
271 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
273 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
367 setOperationAction(ISD::CTLZ, VT, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp155 setOperationAction(ISD::CTLZ, XLenVT, Expand);

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