/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 96 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); 130 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); 187 setOperationAction(ISD::CONCAT_VECTORS, BoolV, Custom); 261 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), 909 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1}); 910 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV}); 956 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SingleV, V1}); 957 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SingleV}); 1044 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1); 1112 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, d [all...] |
H A D | HexagonISelLowering.cpp | 1339 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS, 1493 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE 1542 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); 2903 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
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H A D | HexagonISelDAGToDAGHVX.cpp | 1426 // XXX CONCAT_VECTORS is legal for HVX vectors. Legalizing (lowering) 1430 LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1});
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 395 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 399 CONCAT_VECTORS, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 583 case ISD::CONCAT_VECTORS: 832 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 1089 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 1102 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); 1105 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); 1399 ISD::CONCAT_VECTORS, dl, OtherVT, 1929 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 2052 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); 2127 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 2232 return DAG.getNode(ISD::CONCAT_VECTORS, SDLo [all...] |
H A D | DAGCombiner.cpp | 1608 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 8707 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && 8708 RHS.getOpcode() == ISD::CONCAT_VECTORS && 8748 ISD::CONCAT_VECTORS, DL, VT, 8976 if (N1.getOpcode() == ISD::CONCAT_VECTORS && 8977 N2.getOpcode() == ISD::CONCAT_VECTORS && 9333 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads); 10919 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { 10955 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds); 15414 StoredVal = DAG.getNode(MemVT.isVector() ? ISD::CONCAT_VECTORS [all...] |
H A D | SelectionDAGDumper.cpp | 282 case ISD::CONCAT_VECTORS: return "concat_vectors";
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H A D | SelectionDAG.cpp | 2603 case ISD::CONCAT_VECTORS: { 3930 case ISD::CONCAT_VECTORS: { 4558 case ISD::CONCAT_VECTORS: 5160 case ISD::CONCAT_VECTORS: { 5330 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 5333 N1.getOpcode() == ISD::CONCAT_VECTORS && 5434 if (N2C && N1.getOpcode() == ISD::CONCAT_VECTORS && 5562 case ISD::CONCAT_VECTORS: { 7356 case ISD::CONCAT_VECTORS:
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H A D | LegalizeDAG.cpp | 3022 case ISD::CONCAT_VECTORS: 4561 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps); 4683 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
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H A D | LegalizeIntegerTypes.cpp | 107 case ISD::CONCAT_VECTORS: 1046 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); 1270 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
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H A D | SelectionDAGBuilder.cpp | 415 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 422 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS 3640 // a CONCAT_VECTORS operation. 3651 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); 3669 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); 3670 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); 5538 case ISD::CONCAT_VECTORS:
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H A D | TargetLowering.cpp | 975 case ISD::CONCAT_VECTORS: { 2309 case ISD::CONCAT_VECTORS: {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 1351 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); 1430 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); 1547 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom); 1548 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom); 1549 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom); 1550 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom); 1751 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom); 1752 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom); 1782 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom); 1783 setOperationAction(ISD::CONCAT_VECTORS, MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 278 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom); 279 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom); 280 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 281 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); 282 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom); 283 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom); 284 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 285 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1131 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 1440 Join = DAG.getNode(ISD::CONCAT_VECTORS, S [all...] |
H A D | SIISelLowering.cpp | 276 case ISD::CONCAT_VECTORS: 538 case ISD::CONCAT_VECTORS: 3985 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); 4008 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); 4031 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); 4975 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces); 5736 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 648 setTargetDAGCombine(ISD::CONCAT_VECTORS); 902 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); 3088 SDValue TruncExt = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16, 6638 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, 7027 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1); 7165 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst); 7173 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); 7282 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) { 10422 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy, 11200 return DAG.getNode(ISD::CONCAT_VECTORS, D [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 184 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); 412 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); 7347 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper); 7483 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, 8035 // Also check for these shuffles through CONCAT_VECTORS: we canonicalize 8050 if (ST->hasNEON() && V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) { 8068 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0), 8256 "Unexpected custom CONCAT_VECTORS lowering"); 8258 "CONCAT_VECTORS lowering only supported for MVE"); 8302 // The only time a CONCAT_VECTORS operatio [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 638 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1886 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack() 2189 case ISD::CONCAT_VECTORS:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1008 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand); 1056 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand); 1097 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand); 8010 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops);
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