Searched refs:gOmapInterruptControllerBase (Results 1 - 5 of 5) sorted by relevance

/darwin-on-arm/xnu/pexpert/arm/
H A Dpe_omap335x.h60 #define INTCPS_SYSCONFIG (gOmapInterruptControllerBase + 0x0010)
61 #define INTCPS_SYSSTATUS (gOmapInterruptControllerBase + 0x0014)
62 #define INTCPS_SIR_IRQ (gOmapInterruptControllerBase + 0x0040)
63 #define INTCPS_SIR_IFQ (gOmapInterruptControllerBase + 0x0044)
64 #define INTCPS_CONTROL (gOmapInterruptControllerBase + 0x0048)
65 #define INTCPS_PROTECTION (gOmapInterruptControllerBase + 0x004C)
66 #define INTCPS_IDLE (gOmapInterruptControllerBase + 0x0050)
67 #define INTCPS_IRQ_PRIORITY (gOmapInterruptControllerBase + 0x0060)
68 #define INTCPS_FIQ_PRIORITY (gOmapInterruptControllerBase + 0x0064)
69 #define INTCPS_THRESHOLD (gOmapInterruptControllerBase
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H A Dpe_omap3530.h150 #define INTCPS_SYSCONFIG (gOmapInterruptControllerBase + 0x0010)
151 #define INTCPS_SYSSTATUS (gOmapInterruptControllerBase + 0x0014)
152 #define INTCPS_SIR_IRQ (gOmapInterruptControllerBase + 0x0040)
153 #define INTCPS_SIR_IFQ (gOmapInterruptControllerBase + 0x0044)
154 #define INTCPS_CONTROL (gOmapInterruptControllerBase + 0x0048)
155 #define INTCPS_PROTECTION (gOmapInterruptControllerBase + 0x004C)
156 #define INTCPS_IDLE (gOmapInterruptControllerBase + 0x0050)
157 #define INTCPS_IRQ_PRIORITY (gOmapInterruptControllerBase + 0x0060)
158 #define INTCPS_FIQ_PRIORITY (gOmapInterruptControllerBase + 0x0064)
159 #define INTCPS_THRESHOLD (gOmapInterruptControllerBase
[all...]
H A Dpe_omap335x.c71 vm_offset_t gOmapInterruptControllerBase = 0x0; variable
410 gOmapInterruptControllerBase = ml_io_map(OMAP3_GIC_BASE, PAGE_SIZE);
H A Dpe_omap3430.c80 vm_offset_t gOmapInterruptControllerBase = 0x0; variable
147 gOmapInterruptControllerBase = ml_io_map(OMAP3_GIC_BASE, PAGE_SIZE);
H A Dpe_omap3530.c68 vm_offset_t gOmapInterruptControllerBase = 0x0; variable
135 gOmapInterruptControllerBase = ml_io_map(OMAP3_GIC_BASE, PAGE_SIZE);

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