1/*
2 * OMAP 35xx support
3 */
4
5#ifndef _PEXPERT_OMAP3530_H_
6#define _PEXPERT_OMAP3530_H_
7
8/*
9 * Note, on older OMAP platforms, the size of the NS16550 UARTS
10 * is different, for this one it's 32-bit.
11 */
12
13#define RBR     0x0
14#define IER     0x4
15#define FCR     0x8
16#define LCR     0xC
17#define MCR     0x10
18#define LSR     0x14
19#define MSR     0x18
20#define SCR     0x1C
21
22#define OMAP3_TIMER0_BASE        0x48318000
23#define OMAP3_GIC_BASE           0x48200000
24
25#define OMAP3_L4_PERIPH_BASE    0x49000000
26#define OMAP3_UART_BASE         (OMAP3_L4_PERIPH_BASE + 0x20000)    // This is uart2
27
28#define OMAP3_UART_CLOCK        48000000
29#define OMAP3_UART_BAUDRATE     115200
30
31#define LCR_BKSE	0x80                /* Bank select enable */
32#define LCR_8N1		0x03
33
34#define LSR_DR		0x01                /* Data ready */
35#define LSR_THRE	0x20                /* Xmit holding register empty */
36
37#define MCR_DTR         0x01
38#define MCR_RTS         0x02
39
40#define FCR_FIFO_EN     0x01            /* Fifo enable */
41#define FCR_RXSR        0x02            /* Receiver soft reset */
42#define FCR_TXSR        0x04            /* Transmitter soft reset */
43
44#define LCRVAL LCR_8N1                              /* 8 data, 1 stop, no parity */
45#define MCRVAL (MCR_DTR | MCR_RTS)                  /* RTS/DTR */
46#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR)	/* Clear & enable FIFOs */
47
48#define THR     RBR
49#define DLL     RBR
50#define DLM     IER
51
52/*
53 * DSS/framebuffer stuff
54 */
55#define OMAP3_DSS_BASE      0x48050040
56#define OMAP3_DISPC_BASE    0x48050440
57#define OMAP3_VENC_BASE     0x48050C00
58
59typedef uint32_t u32;
60
61/* DSS Registers */
62struct dss_regs {
63    u32 control;                /* 0x40 */
64    u32 sdi_control;            /* 0x44 */
65    u32 pll_control;            /* 0x48 */
66};
67
68/* DISPC Registers */
69struct dispc_regs {
70    u32 control;                /* 0x40 */
71    u32 config;             /* 0x44 */
72    u32 reserve_2;              /* 0x48 */
73    u32 default_color0;         /* 0x4C */
74    u32 default_color1;         /* 0x50 */
75    u32 trans_color0;           /* 0x54 */
76    u32 trans_color1;           /* 0x58 */
77    u32 line_status;            /* 0x5C */
78    u32 line_number;            /* 0x60 */
79    u32 timing_h;               /* 0x64 */
80    u32 timing_v;               /* 0x68 */
81    u32 pol_freq;               /* 0x6C */
82    u32 divisor;                /* 0x70 */
83    u32 global_alpha;           /* 0x74 */
84    u32 size_dig;               /* 0x78 */
85    u32 size_lcd;               /* 0x7C */
86	u32 gfx_ba0;				/* 0x80 */
87	u32 gfx_ba1;				/* 0x84 */
88	u32 gfx_position;			/* 0x88 */
89	u32 gfx_size;				/* 0x8C */
90	uint8_t unused[16];				/* 0x90 */
91	u32 gfx_attributes;			/* 0xA0 */
92	u32 gfx_fifo_threshold;     /* 0xA4 */
93	u32 gfx_fifo_size_status;   /* 0xA8 */
94	u32 gfx_row_inc;			/* 0xAC */
95	u32 gfx_pixel_inc;			/* 0xB0 */
96	u32 gfx_window_skip;        /* 0xB4 */
97	u32 gfx_table_ba;			/* 0xB8 */
98};
99
100/* Few Register Offsets */
101#define FRAME_MODE_SHIFT            1
102#define TFTSTN_SHIFT                3
103#define DATALINES_SHIFT             8
104
105/* Enabling Display controller */
106#define LCD_ENABLE              1
107#define DIG_ENABLE              (1 << 1)
108#define GO_LCD                  (1 << 5)
109#define GO_DIG                  (1 << 6)
110#define GP_OUT0                 (1 << 15)
111#define GP_OUT1                 (1 << 16)
112
113#define DISPC_ENABLE                (LCD_ENABLE | \
114                         DIG_ENABLE | \
115                         GO_LCD | \
116                         GO_DIG | \
117                         GP_OUT0| \
118                         GP_OUT1)
119
120/* Configure VENC DSS Params */
121#define VENC_CLK_ENABLE             (1 << 3)
122#define DAC_DEMEN               (1 << 4)
123#define DAC_POWERDN             (1 << 5)
124#define VENC_OUT_SEL                (1 << 6)
125#define DIG_LPP_SHIFT               16
126#define VENC_DSS_CONFIG             (VENC_CLK_ENABLE | \
127                         DAC_DEMEN | \
128                         DAC_POWERDN | \
129                         VENC_OUT_SEL)
130/*
131 * Panel Configuration
132 */
133struct panel_config {
134    u32 timing_h;
135    u32 timing_v;
136    u32 pol_freq;
137    u32 divisor;
138    u32 lcd_size;
139    u32 panel_type;
140    u32 data_lines;
141    u32 load_mode;
142    u32 panel_color;
143};
144
145/*
146 * gPIC configuration
147 */
148#define INT_NROF_VECTORS      (96)
149#define MAX_VECTOR            (INT_NROF_VECTORS - 1)
150#define INTCPS_SYSCONFIG      (gOmapInterruptControllerBase + 0x0010)
151#define INTCPS_SYSSTATUS      (gOmapInterruptControllerBase + 0x0014)
152#define INTCPS_SIR_IRQ        (gOmapInterruptControllerBase + 0x0040)
153#define INTCPS_SIR_IFQ        (gOmapInterruptControllerBase + 0x0044)
154#define INTCPS_CONTROL        (gOmapInterruptControllerBase + 0x0048)
155#define INTCPS_PROTECTION     (gOmapInterruptControllerBase + 0x004C)
156#define INTCPS_IDLE           (gOmapInterruptControllerBase + 0x0050)
157#define INTCPS_IRQ_PRIORITY   (gOmapInterruptControllerBase + 0x0060)
158#define INTCPS_FIQ_PRIORITY   (gOmapInterruptControllerBase + 0x0064)
159#define INTCPS_THRESHOLD      (gOmapInterruptControllerBase + 0x0068)
160#define INTCPS_ITR(n)         (gOmapInterruptControllerBase + 0x0080 + (0x20 * (n)))
161#define INTCPS_MIR(n)         (gOmapInterruptControllerBase + 0x0084 + (0x20 * (n)))
162#define INTCPS_MIR_CLEAR(n)   (gOmapInterruptControllerBase + 0x0088 + (0x20 * (n)))
163#define INTCPS_MIR_SET(n)     (gOmapInterruptControllerBase + 0x008C + (0x20 * (n)))
164#define INTCPS_ISR_SET(n)     (gOmapInterruptControllerBase + 0x0090 + (0x20 * (n)))
165#define INTCPS_ISR_CLEAR(n)   (gOmapInterruptControllerBase + 0x0094 + (0x20 * (n)))
166#define INTCPS_PENDING_IRQ(n) (gOmapInterruptControllerBase + 0x0098 + (0x20 * (n)))
167#define INTCPS_PENDING_FIQ(n) (gOmapInterruptControllerBase + 0x009C + (0x20 * (n)))
168#define INTCPS_ILR(m)         (gOmapInterruptControllerBase + 0x0100 + (0x04 * (m)))
169
170/*
171 * Timer.
172 */
173#define GPT1_IRQ        37
174#define TIDR            0x0
175#define TIOCP_CFG       0x10
176#define TISTAT          0x14
177#define TISR            0x18
178#define TIER            0x1C
179#define TWER            0x20
180#define TCLR            0x24
181#define TCRR            0x28
182#define TLDR            0x2C
183#define TTGR            0x30
184#define TWPS            0x34
185#define TMAR            0x38
186#define TCAR1           0x3C
187#define TSICR           0x40
188#define TCAR2           0x44
189
190/* Only for GPTIMER1/2 */
191#define TPIR            0x48
192#define TNIR            0x4C
193#define TCVR            0x50
194#define TOCR            0x54
195#define TOWR            0x58
196
197
198
199
200#endif /* !_PEXPERT_OMAP3530_H_ */
201